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S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C72P9 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-896-dot LCD direct drive capability, flexible 8-bit and 16-bit timer/counters, and serial I/O interface, the S3C72P9 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C72P9's advanced CMOS technology provides for low power consumption and a wide operating voltage range. The S3C72P9 is made by shrinking the KS57C21516. The S3C72P9 is comparable to KS57C21516, both in function and in pin configuration except that S3C72P9 have a 32,768 x8-bit ROM, 1056x4-bit RAM, 12 common selectable and LCD contrast control function.
OTP
The S3C72P9 microcontroller is also available in OTP (One Time Programmable) version, S3P72P9. S3P72P9 microcontroller has an on-chip 32K-byte one-time-programmable EPROM instead of masked ROM. The S3P72P9 is comparable to S3C72P9, both in function and in pin configuration.
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PRODUCT OVERVIEW
S3C72P9/P72P9 (Preliminary Spec)
FEATURES
Memory * * 1,056 x 4-bit RAM (excluding LCD display RAM) 32,768 x 8-bit ROM * 39 I/O Pins * * I/O: 35 pins Input only: 4 pins Interrupts * LCD Controller/Driver * * * * * 56 segments and 16 common terminals 8, 12 and 16 common selectable Internal resistor circuit for LCD bias All dot can be switched on/off LCD contrast control by software Power-Down Modes 8-bit Basic Timer * * 4 interval timer functions Watch-dog timer * * * Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) Subsystem clock stop mode Bit Sequential Carrier * Supports 16-bit serial data transfer in arbitrary format * * Four internal vectored interrupts Four external vectored interrupts Two quasi-interrupts * Watch Timer * Time interval generation: 0.5 s, 3.9 ms at 32768 Hz 4 frequency outputs to BUZ pin Clock source generation for LCD
8-bit Timer/Counter * * * * * Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider Serial I/O interface clock generator
Oscillation Sources * * * * * Crystal, ceramic, or RC for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 0.4 - 6 MHz Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64)
16-Bit Timer/Counter * * * * Programmable 16-bit timer External event counter Arbitrary clock frequency output External clock signal divider
Instruction Execution Times * * * 0.67, 1.33, 10.7 s at 6 MHz 0.95, 1.91, 15.3 s at 4.19 MHz 122 s at 32.768 kHz
Operating Temperature 8-bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source Operating Voltage Range * 1.8 V to 5.5 V * - 40 C to 85 C
Package Type * 100-pin QFP
Memory-Mapped I/O Structure * Data memory bank 15
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S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
BLOCK DIAGRAM
Watchdog Timer P1.0-P1.3/ INT0-INT4 P2.0/CLO P2.1/LCDCK P2.2/LCDSY P3.0/TCLO0 P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 P4.0-P4.3/ COM8-COM11 P5.0-P5.3/ COM12-COM15 P6.0-P6.3/ SEG55-SEG52/ K4-K7 P7.0-P7.3/ SEG51-SEG48 Input Port 1 RESET XIN XOUT Basic Timer
XTIN XTOUT Watch Timer
I/O Port 2 Interrupt Control Block Clock Instruction Register VLC1-VLC5 LCD Driver/ Controller COM0-COM7 P4.0-P4.3/ CO8-COM11 P5.0-P5.3/ COM12-COM15 SEG0-SEG39 P9.3-P6.0/ SEG40-SEG55
I/O Port 3
I/O Port 4
Internal Interrupts
Program Counter
LCD Contrast Controller SIO
I/O Port 5
Instruction Decoder
Program Status Word I/O Port 0 Stack Pointer P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3
I/O Port 6
I/O Port 7
Arithmetic and Logic Unit
8-Bit Timer/ Counter
P8.0-P8.3/ SEG47-SEG44 P9.0-P9.3/ SEG43-SEG40
I/O Port 8 1,056 x 4-Bit Data Memory 32,768 x 8-Bit Program Memory 16-Bit Timer/ Counter
I/O Port 9
Figure 1-1. S3C72P9/P72P9 Simplified Block Diagram
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PRODUCT OVERVIEW
S3C72P9/P72P9 (Preliminary Spec)
PIN ASSIGNMENTS
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P9.3/SEG40 P9.2/SEG41 P9.1/SEG42 P9.0/SEG43 P8.3/SEG44 P8.2/SEG45 P8.1/SEG46 P8.0/SEG47 P7.3/SEG48 P7.2/SEG49 P7.1/SEG50 P7.0/SEG51 P6.3/SEG52/K7 P6.2/SEG53/K6 P6.1/SEG54/K5
SEG4 SEG3 SEG2 SEG1 SEG0 VLC5 VLC4 VLC3 VLC2 VLC1 P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/LCDCK P2.2/LCDSY P3.0/TCLO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3C72P9
(100-QFP-1420C)
Figure 1-2. S3C72P9 100-QFP Pin Assignment Diagram
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P6.0/SEG55/K4 P5.3/COM15 P5.2/COM14 P5.1/COM13 P5.0/COM12 P4.3/COM11 P4.2/COM10 P4.1/COM9 P4.0/COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 P3.3/TCL1 P3.2/TCL0 P3.1/TCLO0
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S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72P9/P72P9 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are assignable by software. Same as port 0 except that port 2 is 3-bit I/O port. Number 11 12 13 14 Share Pin SCK/K0 SO/K1 SI/K2 BUZ/K3
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
I
23 24 25 26 27 28 29 30 31 32 33 42-45 46-49
INT0 INT1 INT2 INT4 CLO LCDCK LCDSY TCLO0 TCLO1 TCL0 TCL1 COM8- COM11 COM12- COM15
I/O
I/O
Same as port 0.
I/O
4-bit I/O ports. 1-, 4-bit or 8-bit read/write and test are possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as P4, P5.
P6.0-P6.3 P7.0-P7.3
I/O
50-53
SEG55/K4- SEG52/K7 SEG51- SEG48 SEG47- SEG44 SEG43- SEG40 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P1.0, P1.1
54-57 P8.0-P8.3 P9.0-P9.3 SCK SO SI BUZ INT0, INT1 I/O I/O I/O I/O I Serial I/O interface clock signal. Serial data output. Serial data input. 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for buzzer signal. External interrupts. The triggering edge for INT0 and INT1 is selectable. I/O Same as P4, P5. 58-61 62-65 11 12 13 14 23, 24
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PRODUCT OVERVIEW
S3C72P9/P72P9 (Preliminary Spec)
Table 1-1. S3C72P9/P72P9 Pin Descriptions (Continued) Pin Name INT2 INT4 CLO LCDCK LCDSY TCLO0 TCLO1 TCL0 TCL1 COM0-COM7 COM8-COM11 COM12-COM15 SEG0-SEG39 SEG40-SEG43 SEG44-SEG47 SEG48-SEG51 SEG52-SEG55 K0-K3 K4-K7 VDD VSS RESET VLC1-VLC5 XIN, XOUT XTIN, XTOUT TEST - - I - - - I Main power supply. Ground. Reset signal. LCD power supply. Crystal, Ceramic or RC oscillator pins for system clock. Crystal oscillator pins for subsystem clock. Test signal input. (must be connected to VSS) I/O External interrupt. The triggering edge is selectable. O I/O LCD segment signal output. Pin Type I I I/O I/O I/O I/O I/O I/O I/O O I/O Description Quasi-interrupt with detection of rising or falling edges. External interrupt with detection of rising or falling edges. Clock output . LCD clock output for display expansion. LCD synchronization clock output for display expansion. Timer/counter 0 clock output. Timer/counter 1 clock output. External clock input for timer/counter 0. External clock input for timer/counter 1. LCD common signal output. Number 25 26 27 28 29 30 31 32 33 34-41 42-45 46-49 5-1, 100-66 65-62 61-58 57-54 53-50 11-14 50-53 15 16 22 10-6 18, 17 20, 21 19 Share Pin P1.2 P1.3 P2.0 P2.1 P2.2 P3.0 P3.1 P3.2 P3.3 - P4.0-P4.3 P5.0-P5.3 - P9.3-P9.0 P8.3-P8.0 P7.3-P7.0 P6.3/K7-P6.0/K4 P0.0-P0.3 P6.0-P6.3 - - - - - - -
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
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S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
Table 1-2. Overview of S3C72P9/P72P9 Pin Data Pin Names P0.1, P0.3 P0.0, P0.2 P1.0-P1.3 P2.0-P2.2 P3.0-P3.1 P3.2-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.3 P8.0-P8.3 P9.0-P9.3 COM0-COM7 SEG0-SEG39 VDD VSS RESET VLC1-VLC5 XIN, XOUT XTIN, XTOUT TEST Share Pins SO/K1, BUZ/K3 SCK/K0, SI/K2 INT0-INT2, INT4 CLO, LCDCK, LCDSY TCLO0, TCLO1 TCL0, TCL1 COM8-COM11 COM12-COM15 SEG55/K4-SEG52/K7 SEG51-SEG48 SEG47-SEG44 SEG43-SEG40 - - - - - - - - - I/O Type I/O I/O I I/O I/O I/O I/O I/O I/O I/O O O - - I - - - I Reset Value Input Input Input Input Input Input Input Input Input Input High High - - - - - - - Circuit Type E-1 E-2 A-3 E E E-1 H-13 H-16 H-13 H-13 H-3 H-15 - - B - - - -
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PRODUCT OVERVIEW
S3C72P9/P72P9 (Preliminary Spec)
PIN CIRCUIT DIAGRAMS
VDD VDD P-Channel In N-Channel In Schmitt Trigger
Pull-up Resistor
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD Pull-Up Resistor P-Channel In Pull-Up Resistor Enable Data
VDD
P-Channel Out
Output Disable Schmitt Trigger
N-Channel
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
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S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
VDD PNE Pull-up Resistor
VDD
P-CH Data Output Disable N-CH
Resistor Enable I/O
Figure 1-7. Pin Circuit Type E
VDD PNE Pull-up Resistor
VDD
P-CH Data Output Disable N-CH
Resistor Enable I/O
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-1
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PRODUCT OVERVIEW
S3C72P9/P72P9 (Preliminary Spec)
VDD PNE Pull-up Resistor
VDD
P-CH Data Output Disable N-CH
Resistor Enable I/O
Schmitt Trigger
Figure 1-9. Pin Circuit Type E-2
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S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
VDD
VLC1
COM
Out
VLC4
VLC5
Figure 1-10. Pin Circuit Type H-3
VDD Pull-up Resistor Pull-up Resistor Enable COM/SEG Output Disable Data Type H-3 P-CH
Type C
I/O
Figure 1-11. Pin Circuit Type H-13
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PRODUCT OVERVIEW
S3C72P9/P72P9 (Preliminary Spec)
VDD
VLC2
SEG
Out
VLC3
VLC5
Figure 1-12. Pin Circuit Type H-15
VDD Pull-up Resistor Pull-up Resistor Enable SEG Output Disable Data Type H-15 P-CH
Type C
I/O
Schmitt Trigger
Figure 1-13. Pin Circuit Type H-16
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
2
OVERVIEW
ADDRESS SPACES
PROGRAM MEMORY (ROM)
ROM maps for S3C72P9 devices are mask programmable at the factory. In its standard configuration, the device's 32,768 x 8-bit program memory has three areas that are directly addressable by the program counter (PC): -- 16-byte area for vector addresses -- 96-byte instruction reference area -- 16-byte general-purpose area -- 32,640-byte general-purpose area General-purpose Program Memory Two program memory areas are allocated for general-purpose use: One area is 16 bytes in size and the other is 32,640 bytes. Vector Addresses A 16-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the corresponding service routines. The 16-byte area can be used alternately as general-purpose ROM. REF Instructions Locations 0020H-007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte instructions, and one 3-byte instructions which are stored in the look-up table. Unused look-up table addresses can be used as general-purpose ROM. Table 2-1. Program Memory Address Ranges ROM Area Function Vector address area General-purpose program memory REF instruction look-up table area General-purpose program memory Address Ranges 0000H-000FH 0010H-001FH 0020H-007FH 0080H-7FFFH Area Size (in Bytes) 16 16 96 32,640
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
GENERAL-PURPOSE MEMORY AREAS The 16-byte area at ROM locations 0010H-001FH and the 32,640-byte area at ROM locations 0080H-7FFFH are used as general-purpose program memory. Unused locations in the vector address area and REF instruction look-up table areas can be used as general-purpose program memory. However, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the ROM. VECTOR ADDRESS AREA The 16-byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines. 16-byte vector addresses are organized as follows: EMB PC7 ERB PC6 PC13 PC5 PC12 PC4 PC11 PC3 PC10 PC2 PC9 PC1 PC8 PC0
To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the next page explain how to do this.
0000H Vector Address Area (16 Bytes) 000FH 0010H General- Purpose Area (16 Bytes) 001FH 0020H Instruction Reference Area (96 Bytes) 007FH 0080H 0000H 0002H 0004H 0006H 0008H 000AH General-Purpose Area (32,640 Bytes) 000CH 000EH 7FFFH
7
6
5
4
3
2
1
0
RESET INTB/INT4 INT0 INT1 INTS INTT0 INTT1 INTK
Figure 2-1. ROM Address Structure
Figure 2-2. Vector Address Map
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
+ PROGRAMMING TIP -- Defining Vectored Interrupts
The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. When all vector interrupts are used: ORG ; VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 VENT6 VENT7 1,0,RESET 0,0,INTB 0,0,INT0 0,0,INT1 0,0,INTS 0,0,INTT0 0,0,INTT1 0,0,INTK 0000H ; EMB 1, ERB 0; Jump to RESET address by RESET ; EMB 0, ERB 0; Jump to INTB address by INTB ; EMB 0, ERB 0; Jump to INT0 address by INT0 ; EMB 0, ERB 0; Jump to INT1 address by INT1 ; EMB 0, ERB 0; Jump to INTS address by INTS ; EMB 0, ERB 0; Jump to INTT0 address by INTT0 ; EMB 0, ERB 0; Jump to INTT1 address by INTT1 ; EMB 0, ERB 0; Jump to INTK address by INTK
2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations: ORG ; VENT0 VENT1 ORG VENT3 VENT4 ; ORG ; VENT6 VENT7 ; ORG 0010H 0,0,INTT1 0,0,INTK ; EMB 0, ERB 0; Jump to INTT1 address by INTT1 ; EMB 0, ERB 0; Jump to INTK address by INTK 000CH ; INTT0 interrupt not used 1,0,RESET 0,0,INTB 0006H 0,0,INT1 0,0,INTS ; EMB 1, ERB 0; Jump to RESET address by RESET ; EMB 0, ERB 0; Jump to INTB address by INTB ; INT0 interrupt not used ; EMB 0, ERB 0; Jump to INT1 address by INT1 ; EMB 0, ERB 0; Jump to INTS address by INTS 0000H
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Defining Vectored Interrupts (Continued)
3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a ORG instruction as in Example 2, a CPU malfunction will occur: ORG ; VENT0 VENT1 VENT3 VENT4 VENT5 VENT6 VENT7 ; ORG ; General-purpose ROM area ; In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to occur. 0010H 1,0,RESET 0,0,INTB 0,0,INT1 0,0,INTS 0,0,INTT0 0,0,INTT1 0,0,INTK ; EMB 1, ERB 0; Jump to RESET address by RESET ; EMB 0, ERB 0; Jump to INTB address by INTB ; EMB 0, ERB 0; Jump to INT1 address by INT0 ; EMB 0, ERB 0; Jump to INTS address by INT1 ; EMB 0, ERB 0; Jump to INTT0 address by INTS ; EMB 0, ERB 0; Jump to INTT1 address by INTT0 ; EMB 0, ERB 0; Jump to INTK address by INTT1 0000H
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
INSTRUCTION REFERENCE AREA Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020H-007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table. Locations in the REF look-up table may contain two 1-byte instructions, one 2-byte instruction, or one 3-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are three ways to the REF instruction: By using REF instructions you can execute instructions larger than one byte. In summary, there are three ways you can use the REF instruction: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions, -- Branching to any location by referencing a branch instruction stored in the look-up table, -- Calling subroutines at any location by referencing a call instruction stored in the look-up table.
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Using the REF Look-Up Table
Here is one example of how to use the REF instruction look-up table: ORG ; JMAIN KEYCK WATCH INCHL TJP BTSF TCALL LD INCS * * * ABC ; MAIN NOP NOP * * * REF REF REF REF REF * * * KEYCK JMAIN WATCH INCHL ABC ; BTSF KEYFG (1-byte instruction) ; KEYFG = 1, jump to MAIN (1-byte instruction) ; KEYFG = 0, CALL CLOCK (1-byte instruction) ; LD @HL,A ; INCS HL ; LD EA,#00H (1-byte instruction) LD ORG EA,#00H 0080 ; 47, EA #00H MAIN KEYFG CLOCK @HL,A HL ; 0, MAIN ; 1, KEYFG CHECK ; 2, Call CLOCK ; 3, (HL) A 0020H
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
DATA MEMORY (RAM)
OVERVIEW In its standard configuration, the 1298 x 4-bit data memory has four areas: -- 32 x 4-bit working register area in bank 0 -- 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area -- 256 x 4-bit general-purpose area in bank 1 -- 224 x 4-bit area for LCD data in bank 2 -- 32 x 4-bit general-purpose area in bank 2 -- 256 x 4-bit general-purpose area in bank 3 -- 256 x 4-bit general-purpose area in bank 4 -- 128 x 4-bit area in bank 15 for memory-mapped I/O addresses To make it easier to reference, the data memory area has six memory banks -- bank 0, bank 1, bank 2, bank 3, bank 4 and bank 15. The select memory bank instruction (SMB) is used to select the bank you want to select as working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power RESET. However, when RESET signal is generated in power-down mode, the most of data memory contents are held.
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
000H
Working Registers (32 x 4 Bits) General-purpose Registers and Stack Area (224 x 4 Bits) General-purpose Registers (256 x 4 Bits) LCD Data Registers (224 x 4Bits) General-purpose Registers (32 x 4 Bits) Bank 0
01FH 020H
0FFH 100H
Bank 1
1FFH 200H
Bank 2
2FFH 300H
3FFH 400H
General-purpose Registers (256 x 4 Bits) General-purpose Registers (256 x 4 Bits)
Bank 3
Bank 4
4FFH F80H
Memory-mapped I/O Address Registers (128 x 4 Bits)
Bank 15
FFFH
Figure 2-3. Data Memory (RAM) Map
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
Memory Banks 0, 1, 2, 3, 4 and 15 Bank 0 (000H-0FFH) The lowest 32 nibbles of bank 0 (000H-01FH) are used as working registers; the next 224 nibbles (020H-0FFH) can be used both as stack area and as general-purpose data memory. Use the stack area for implementing subroutine calls and returns, and for interrupt processing. Bank 1 is used for general-purpose. The 224 nibbles of bank 2 are for display registers or general-purpose use; locations 2xE and 2xF (x = 0-F) are for general-purpose use in bank 2. Detailed map on bank 2 is shown in Section 12 LCD Controller/Driver. Bank 3 is used for general-purpose. Bank 4 is used for general-purpose. The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed RAM locations for each peripheral hardware address are mapped into this area.
Bank 1 Bank 2
(100H-1FFH) (200H-2FFH)
Bank 3 Bank 4 Bank 15
(300H-3FFH) (400H-4FFH) (F80H-FFFH)
Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, 2, 3, 4 or 15. When the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. With direct addressing, you can access locations 000H-07FH of bank 0 and bank 15. With indirect addressing, only bank 0 (000H-0FFH) can be accessed. When the EMB flag is set to logic one, all four data memory banks can be accessed according to the current SMB value. For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to address RAM locations, remember to use the even-numbered register address as the instruction operand. Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 2. Register locations in this area that are not used to store LCD data can be assigned to general-purpose use.
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
Table 2-2. Data Memory Organization and Addressing Addresses 000H-01FH 020H-0FFH 100H-1FFH 200H-2FFH 300H-3FFH 400H-4FFH F80H-FFFH Register Areas Working registers Stack and general-purpose registers General-purpose registers Display registers and general-purpose registers General-purpose registers General-purpose registers I/O-mapped hardware registers 1 2 3 4 15 1 1 1 1 0, 1 1 2 3 4 15 Bank 0 EMB Value 0, 1 SMB Value 0
+ PROGRAMMING TIP -- Clearing Data Memory Banks 0 and 1
Clear banks 0 and 1 of the data memory area: RAMCLR SMB LD LD RMCL1 LD INCS JR ; SMB LD RMCL0 LD INCS JR 0 HL,#10H @HL,A HL RMCL0 ; RAM (010H-0FFH) clear 1 HL,#00H A,#0H @HL,A HL RMCL1 ; RAM (100H-1FFH) clear
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
WORKING REGISTERS Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. Unused registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4bit units or, using paired registers, as 8-bit units.
000H A 001H E 002H L 003H H 004H X 005H Data Memory Bank 0 W 006H Z 007H Y 008H A ...Y 00FH 010H A ...Y 017H 018H A ...Y 01FH Register Bank 1 Register Bank 2 Register Bank 3 Working Register Bank 0
Figure 2-4. Working Register Map
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
Working Register Banks For addressing purposes, the working register area is divided into four register banks -- bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection instruction (SRBn) and by setting the status of the register bank enable flag (ERB). Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing. Table 2-3. Working Register Organization and Addressing ERB Setting 3 0 1 0 0 2 0 0 SRB Settings 1 x 0 0 1 1
NOTE: 'x' means don't care.
Selected Register Bank 0 x 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3
Paired Working Registers Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks.
(MSB) Y
(LSB)
(MSB) Z
(LSB)
W
X
H
L
E
A
Figure 2-5. Register Pair Configuration
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
Special-Purpose Working Registers Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also be used as a 1-bit accumulator. 8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction.
C
1-Bit Accumulator
A
4-Bit Accumulator
EA
8-Bit Accumulator
Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction.
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Selecting the Working Register Area
The following examples show the correct programming method for selecting working register area: 1. When ERB = "0": VENT2 ; INT0 PUSH SRB PUSH PUSH PUSH PUSH SMB LD LD LD INCS LD LD POP POP POP POP POP IRET 1,0,INT0 SB 2 HL WX YZ EA 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA EA YZ WX HL SB ; EMB 1, ERB 0, Jump to INT0 address ; ; ; ; ; ; PUSH current SMB, SRB Instruction does not execute because ERB = "0" PUSH HL register contents to stack PUSH WX register contents to stack PUSH YZ register contents to stack PUSH EA register contents to stack
; ; ; ; ;
POP EA register contents from stack POP YZ register contents from stack POP WX register contents from stack POP HL register contents from stack POP current SMB, SRB
The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values, as shown in Example 2 below. 2. When ERB = "1": VENT2 ; INT0 PUSH SRB SMB LD LD LD INCS LD LD POP IRET 1,1,INT0 SB 2 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA SB ; EMB 1, ERB 1, Jump to INT0 address ; Store current SMB, SRB ; Select register bank 2 because of ERB = "1"
; Restore SMB, SRB
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
STACK OPERATIONS
STACK POINTER (SP) The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always remain cleared to logic zero. F80H F81H SP3 SP7 SP2 SP6 SP1 SP5 "0" SP4
There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack. The program counter contents and program status word are stored in the stack area prior to the execution of a CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out) type. The stack area is located in general-purpose data memory bank 0. During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed. The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the enable memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00H. This sets the first register of the stack area to 0FFH. NOTE A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. To do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly.
+ PROGRAMMING TIP -- Initializing the Stack Pointer
To initialize the stack pointer (SP): 1. When EMB = "1": SMB LD LD 2. When EMB = "0": LD LD EA,#00H SP,EA ; Memory addressing area (00H-7FH, F80H-FFFH) 15 EA,#00H SP,EA ; Select memory bank 15 ; Bit 0 of SP is always cleared to "0" ; Stack area initial address (0FFH) (SP) - 1
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number determined by the type of push operation and then points to the next available stack location. PUSH Instructions A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. After the PUSH has executed, the SP is decremented by two and points to the next available stack location. CALL Instructions When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to the number of levels permitted in the stack. Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is decremented by six and points to the next available stack location. During an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area.
PUSH (After PUSH, S
SP - 2)
CALL, LCALL (After CALL or LCALL, SP SP - 6 SP - 5 SP - 4 SP - 3 0 PC11 - PC8 PC14 - PC12 PC3 - PC0 PC7 - PC4 0 0
SP - 6) SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP
INTERRUPT (When INT is acknowledged, SP SP - 6) PC11 - PC8 0 PC14 - PC12 PC3 - PC0 PC7 - PC4 IS1 C IS0 EMB ERB PSW SC2 SC1 SC0
SP - 2 SP - 1 SP
Lower Register Upper Register
SP - 2 SP - 1 SP
EMB ERB PSW 0 0 0
0
Figure 2-7. Push-Type Stack Operations
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by the type of operation and points to the next free stack location. POP Instructions A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. After the POP has executed, the SP is incremented by two and points to the next free stack location. RET and SRET Instructions The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and the ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack location. IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has executed, the SP is incremented by six and points to the next free stack location.
(SP SP SP + 1 SP + 2
POP SP + 2) SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0
RET or SRET (SP SP + 6) PC11 - PC8 PC14 - PC12 PC3 - PC0 PC7 - PC4 EMB ERB PSW 0 0 0 0 SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 IS1 C 0
(SP
IRET SP + 6)
Lower Register Upper Register
PC11 - PC8 PC14 - PC12 PC3 - PC0 PC7 - PC4 IS0 EMB ERB PSW SC2 SC1 SC0
Figure 2-8. Pop-Type Stack Operations
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
BIT SEQUENTIAL CARRIER (BSC)
The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to logic zero. Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the L register. BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately. If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3. Table 2-4. BSC Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H Bit 3 BSC0.3 BSC1.3 BSC2.3 BSC3.3 Bit 2 BSC0.2 BSC1.2 BSC2.2 BSC3.2 Bit 1 BSC0.1 BSC1.1 BSC2.1 BSC3.1 Bit 0 BSC0.0 BSC1.0 BSC2.0 BSC3.0
+ PROGRAMMING TIP -- Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin: BITS SMB LD LD LD LD SMB LD AGN LDB LDB INCS JR RET EMB 15 EA,#37H BSC0,EA EA,#59H BSC2,EA 0 L,#0H C,BSC0.@L P3.0,C L AGN ; ; ; P3.0 C ; ; BSC0 A, BSC1 E ; ; BSC2 A, BSC3 E
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
PROGRAM COUNTER (PC)
A 14-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a reset operation or an interrupt occurs, bits PC13 through PC0 are set to the vector address. Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1byte REF instruction which is used to reference instructions stored in the ROM.
PROGRAM STATUS WORD (PSW)
The program status word (PSW) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW values are mapped as follows: (MSB) FB0H FB1H IS1 C IS0 SC2 EMB SC1 (LSB) ERB SC0
The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value of the enable memory bank (EMB) flag. Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the interrupt has been processed, the PSW values are popped from the stack back to the PSW address. When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to logical zero. Table 2-5. Program Status Word Bit Descriptions PSW Bit Identifier IS1, IS0 EMB ERB C SC2, SC1, SC0 Description Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag Program skip flags Bit Addressing 1, 4 1 1 1 8 Read/Write R/W R/W R/W R/W R
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S3C72P9/P72P9 (Preliminary Spec)
INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control instructions. By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined by the IPR. When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruction, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings. Table 2-6. Interrupt Status Flag Bit Settings IS1 Value 0 0 1 1 IS0 Value 0 1 0 1 Status of Currently Executing Process 0 1 2 - Effect of IS0 and IS1 Settings on Interrupt Request Control All interrupt requests are serviced. Only high-priority interrupt(s) as determined in the interrupt priority register (IPR) are serviced. No more interrupt requests are serviced. Not applicable; these bit settings are undefined.
Since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI instruction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI instruction to re-enable interrupt processing.
+ PROGRAMMING TIP -- Setting ISx Flags for Interrupt Processing
The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing: INTB DI BITR BITS EI IS1 IS0 ; Disable interrupt ; IS1 0 ; Allow interrupts according to IPR priority level ; Enable interrupt
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
EMB FLAG (EMB) The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it controls the addressing mode for data memory banks 0, 1, 2, 3, 4 or 15. When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H-07FH of memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", the general-purpose areas of bank 0, 1, 2, 3, 4 and 15 can be accessed by using the appropriate SMB value.
+ PROGRAMMING TIP -- Using the EMB Flag to Select Memory Banks
EMB flag settings for memory bank selection: 1. When EMB = "0": SMB LD LD LD SMB LD LD SMB LD LD 2. When EMB = "1": SMB LD LD LD SMB LD LD SMB LD LD 1 A,#9H 90H,A 34H,A 0 90H,A 34H,A 15 20H,A 90H,A ; (190H) A, bank 1 is selected ; (134H) A, bank 1 is selected ; Select memory bank 0 ; (090H) A, bank 0 is selected ; (034H) A, bank 0 is selected ; Select memory bank 15 ; Program error, but assembler does not detect it ; (F90H) A, bank 15 is selected ; Select memory bank 1 1 A,#9H 90H,A 34H,A 0 90H,A 34H,A 15 20H,A 90H,A ; (F90H) A, bank 15 is selected ; (034H) A, bank 0 is selected ; Non-essential instruction since EMB = "0" ; (F90H) A, bank 15 is selected ; (034H) A, bank 0 is selected ; Non-essential instruction, since EMB = "0" ; (020H) A, bank 0 is selected ; (F90H) A, bank 15 is selected ; Non-essential instruction since EMB = "0"
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (SRB). When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is executed. During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions.
+ PROGRAMMING TIP -- Using the ERB Flag to Select Register Banks
ERB flag settings for register bank selection: 1. When ERB = "0": SRB LD LD SRB LD SRB LD 2. When ERB = "1": SRB LD LD SRB LD SRB LD 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; Register bank 1 is selected ; Bank 1 EA #34H ; Bank 1 HL Bank 1 EA ; Register bank 2 is selected ; Bank 2 YZ BANK2 EA ; Register bank 3 is selected ; Bank 3 WX Bank 3 EA 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; Register bank 0 is selected (since ERB = "0", the SRB is configured to bank 0) ; Bank 0 EA #34H ; Bank 0 HL EA ; Register bank 0 is selected ; Bank 0 YZ EA ; Register bank 0 is selected ; Bank 0 WX EA
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESS SPACES
SKIP CONDITION FLAGS (SC2, SC1, SC0) The skip condition flags SC2, SC1, and SC0 in the PSW indicate the current program skip conditions and are set and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed. CARRY FLAG (C) The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations involving bit-addressed data memory. If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag. Table 2-7. Valid Carry Flag Manipulation Instructions Operation Type Direct manipulation SCF RCF CCF BTST C Bit transfer LDB (operand) (1),C LDB C,(operand) (1) Boolean manipulation BAND C,(operand) (1) BOR C,(operand) (1) BXOR C,(operand) (1) Interrupt routine Return from interrupt INTn (2) IRET Instructions Carry Flag Manipulation Set carry flag to "1". Clear carry flag to "0" (reset carry flag). Invert carry flag value (complement carry flag). Test carry and skip if C = "1". Load carry flag value to the specified bit. Load contents of the specified bit to carry flag. AND the specified bit with contents of carry flag and save the result to the carry flag. OR the specified bit with contents of carry flag and save the result to the carry flag. XOR the specified bit with contents of carry flag and save the result to the carry flag. Save carry flag to stack with other PSW bits. Restore carry flag from stack with other PSW bits.
NOTES: 1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b. 2. 'INTn' refers to the specific interrupt being executed and is not an instruction.
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ADDRESS SPACES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Using the Carry Flag as a 1-Bit Accumulator
1. Set the carry flag to logic one: SCF LD LD ADC EA,#0C3H HL,#0AAH EA,HL ; C 1 ; EA #0C3H ; HL #0AAH ; EA #0C3H + #0AAH + #1H, C 1
2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0: LD LDB BAND LDB H,#3H C,@H+0FH.3 C,P3.3 P5.0,C ; Set the upper four bits of the address to the H register ; value ; C bit 3 of 3FH ; C C AND P3.3 ; Output result from carry flag to P5.0
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESSING MODES
3
OVERVIEW
ADDRESSING MODES
The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the addressable area in the RAM is restricted to specific locations. The EMB flag works in connection with the select memory bank instruction, SMBn. You will recall that the SMBn instruction is used to select RAM bank 0, 1, 2, 3, 4 or 15. The SMB setting is always contained in the upper four bits of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0, 1, 2, 3, 4 or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. Several RAM locations are addressable at all times, regardless of the current EMB flag setting. Here are a few guidelines to keep in mind regarding data memory addressing: -- When you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. -- Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing. -- With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
3-1
ADDRESSING MODES
S3C72P9/P72P9 (Preliminary Spec)
RAM Areas 000H 01FH 020H 07FH 080H
Addressing Mode
DA DA.b EMB = 0 EMB = 1
@HL @H+DA.b EMB = 0 EMB = 1
@WX @WL X
mema.b X
memb.@L X
Working Registers
SMB = 0 Bank 0 (General Registers and Stack) Bank 1 (General Registers)
SMB = 0
0FFH 100H
SMB = 1
SMB = 1
1FFH 200H Bank 2 (Display Registers & General Registers) 2FFH 300H Bank 3 (General Registers) 3FFH 400H Bank 4 (General Registers) 4FFH F80H FB0H FBFH FC0H SMB = 4 SMB = 4 SMB = 3 SMB = 3 SMB = 2 SMB = 2
Bank 15 (Peripheral Hardware Registers)
SMB = 15
SMB = 15
FF0H FFFH NOTES: 1. 'X' means don't care. 2. Blank columns indicate RAM areas that are not addressable, given the addressing method and enable memory bank (EMB) flag setting shown in the column headers.
Figure 3-1. RAM Address Structure
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S3C72P9/P72P9 (Preliminary Spec)
ADDRESSING MODES
EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine has completed. At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR) despite the current SMB setting.
+ PROGRAMMING TIP -- Initializing the EMB and ERB Flags
The following assembly instructions show how to initialize the EMB and ERB flag settings: ORG VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 VENT6 VENT7 * * * BITR 0000H 0,1,INTB 0,1,INT0 0,1,INT1 0,1,INTS 0,1,INTT0 0,1,INTT1 0,1,INTK ; ROM address assignment ; EMB 0, ERB 1; Jump to INTB address by INTB ; EMB 0, ERB 1; Jump to INT0 address by INT0 ; EMB 0, ERB 1; Jump to INT1 address by INT1 ; EMB 0, ERB 1; Jump to INTS address by INTS ; EMB 0, ERB 1; Jump to INTT0 address by INTT0 ; EMB 0, ERB 1; Jump to INTT1 address by INTT1 ; EMB 0, ERB 1; Jump to INTK address by INTK
1,0,RESET ; EMB 1, ERB 0; Jump to RESET address by RESET
RESET
EMB
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ADDRESSING MODES
S3C72P9/P72P9 (Preliminary Spec)
ENABLE MEMORY BANK SETTINGS EMB = "1" When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by the select memory bank (SMB) value (0, 1, 2, 3, 4 or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and indirect addressing modes. The addressable RAM areas when EMB = "1" are as follows: If SMB = 0, If SMB = 1, If SMB = 2, If SMB = 3, If SMB = 4, If SMB = 15, EMB = "0" When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. If EMB = "0", the addressable area is restricted to locations 000H-07FH in bank 0 and to locations F80H-FFFH in bank 15 for direct addressing. For indirect addressing, only locations 000H-0FFH in bank 0 are addressable, regardless of SMB value. To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to "1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of ROM address 0000H. EMB-Independent Addressing At any time, several areas of the data memory can be addressed independent of the current status of the EMB flag. These exceptions are described in Table 3-1. 000H-0FFH 100H-1FFH 200H-2FFH 300H-3FFH 400H-4FFH F80H-FFFH
Table 3-1. RAM Addressing Not Affected by the EMB Value Address 000H-0FFH Addressing Method 4-bit indirect addressing using WX and WL register pairs; 8-bit indirect addressing using SP 1-bit direct addressing 1-bit indirect addressing using the L register Affected Hardware Not applicable Program Examples LD PUSH POP BITS BITR A,@WX
FB0H-FBFH FF0H-FFFH FC0H-FFFH
PSW, SCMOD, IEx, IRQx, I/O BSC, I/O
EMB IE4
BTST FC3H.@L BAND C,P3.@L
3-4
S3C72P9/P72P9 (Preliminary Spec)
ADDRESSING MODES
SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in Figure 3-2. During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB instruction. You later restore the value to the SB using the POP SB instruction.
SMB (F83H) SB Register SMB 3 SMB 2 SMB 1 SMB 0 0
SRB (F82H) 0 SRB 1 SRB 0
Figure 3-2. SMB and SRB Values in the SB Register SELECT REGISTER BANK (SRB) INSTRUCTION The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3. One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set using the 'SRB n' instruction. The current SRB value is retained until another register is requested by program software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls. RESET clears the 4-bit SRB value to logic zero. SELECT MEMORY BANK (SMB) INSTRUCTION To select one of the six available data memory banks, you must execute an SMB n instruction specifying the number of the memory bank you want (0, 1, 2, 3, 4 or 15). For example, the instruction 'SMB 1' selects bank 1 and 'SMB 15' selects bank 15. (And remember to enable the selected memory bank by making the appropriate EMB flag setting). The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB value to logic zero. The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls.
3-5
ADDRESSING MODES
S3C72P9/P72P9 (Preliminary Spec)
DIRECT AND INDIRECT ADDRESSING
1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. Indirect addressing specifies a memory location that contains the required direct address. The KS57 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM address must always be used as the instruction operand. 1-BIT ADDRESSING Table 3-2. 1-Bit Direct and Indirect RAM Addressing Operand Notation DA.b Addressing Mode Description Direct: bit is indicated by the RAM address (DA), memory bank selection, and specified bit number (b). EMB Flag Setting 0 Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank 0 Bank 15 Hardware I/O Mapping - All 1-bit addressable peripherals (SMB = 15)
1 mema.b Direct: bit is indicated by addressable area (mema) and bit number (b). Indirect: address is indicated by the upper 10 bits of RAM area (memb) and the upper two bits of register L, and bit is indicated by the lower two bits of register L. Indirect: bit is indicated by the lower four bits of the address (DA), memory bank selection, and the H register identifier. x
000H-FFFH FB0H-FBFH FF0H-FFFH FC0H-FFFH
SMB = 0, 1, 2, 3, 4, 15 Bank 15 IS0, IS1, EMB, ERB, IEx, IRQx, Pn.n BSCn.x Pn.n
memb.@L
x
Bank 15
@H + DA.b
0
000H-0FFH
Bank 0
-
1
000H-FFFH
SMB = 0, 1, 2, 3, 4, 15
All 1-bit addressable peripherals (SMB = 15)
NOTE: 'x' means don't care.
3-6
S3C72P9/P72P9 (Preliminary Spec)
ADDRESSING MODES
+ PROGRAMMING TIP -- 1-Bit Addressing Modes
1-Bit Direct Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 2. If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG ; BFLAG ; CFLAG ; BFLAG ; P3.0 ; 34H.3 1 85H.3 1 If 0BAH.0 = 1, skip Else if 0BAH.0 = 0, 085H.3 1 FF3H.0 (P3.0) 1 34H.3 85H.3 0BAH.0 0 AFLAG ; BFLAG ; CFLAG ; BFLAG ; P3.0 ; 34H.3 1 F85H.3 1 If FBAH.0 = 1, skip Else if, FBAH.0 = 0, F85H.3 (BMOD.3) 1 FF3H.0 (P3.0) 1
3-7
ADDRESSING MODES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- 1-Bit Addressing Modes (Continued)
1-Bit Indirect Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 2. If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG ; H #0BH ; If 0BAH.0 = 1, 0BAH.0 0 and skip ; Else if 0BAH.0 = 0, 0BAH.0 1 34H.3 85H.3 0BAH.0 0 H,#0BH; @H+CFLAG CFLAG ; H #0BH ; If 0BAH.0 = 1, 0BAH.0 0 and skip Else if 0BAH.0 = 0, FBAH.0 1
3-8
S3C72P9/P72P9 (Preliminary Spec)
ADDRESSING MODES
4-BIT ADDRESSING Table 3-3. 4-Bit Direct and Indirect RAM Addressing Operand Notation DA Addressing Mode Description Direct: 4-bit address indicated by the RAM address (DA) and the memory bank selection 1 @HL Indirect: 4-bit address indicated by the memory bank selection and register HL 0 EMB Flag Setting 0 Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank 0 Bank 15 Hardware I/O Mapping - All 4-bit addressable peripherals (SMB = 15) -
000H-FFFH 000H-0FFH
SMB = 0, 1, 2, 3, 4, 15 Bank 0
1
000H-FFFH
SMB = 0, 1, 2, 3, 4, 15
@WX @WL
Indirect: 4-bit address indicated by register WX Indirect: 4-bit address indicated by register WL
x x
000H-0FFH 000H-0FFH
Bank 0 Bank 0
All 4-bit addressable peripherals (SMB = 15) -
NOTE: 'x' means don't care.
3-9
ADDRESSING MODES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- 4-Bit Addressing Modes
4-Bit Direct Addressing 1. If EMB = "0": ADATA BDATA EQU EQU SMB LD SMB LD LD 2. If EMB = "1": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 A,P3 0 ADATA,A BDATA,A ; (046H) A ; (08EH) A ; A (P3) 46H 8EH 15 A,P3 0 ADATA,A BDATA,A ; Non-essential instruction, since EMB = "0" ; A (P3) ; Non-essential instruction, since EMB = "0" ; (046H) A ; (F8EH (LCON)) A
3-10
S3C72P9/P72P9 (Preliminary Spec)
ADDRESSING MODES
+ PROGRAMMING TIP -- 4-Bit Addressing Modes (Continued)
4-Bit Indirect Addressing (Example 1) 1. If EMB = "0", compare bank 0 locations 040H-046H with bank 0 locations 060H-066H: ADATA BDATA EQU EQU SMB LD LD COMP LD CPSE SRET DECS JR RET 2. If EMB = "1", compare bank 0 locations 040H-046H to bank 1 locations 160H-166H: ADATA BDATA EQU EQU SMB LD LD COMP LD CPSE SRET DECS JR RET L COMP 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL ; A bank 0 (040H-046H) ; If bank 1 (160H-166H) = A, skip L COMP 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL ; A bank 0 (040H-046H) ; If bank 0 (060H-066H) = A, skip ; Non-essential instruction, since EMB = "0"
3-11
ADDRESSING MODES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- 4-Bit Addressing Modes (Concluded)
4-Bit Indirect Addressing (Example 2) 1. If EMB = "0", exchange bank 0 locations 040H-046H with bank 0 locations 060H-066H: ADATA BDATA EQU EQU SMB LD LD TRANS LD XCHD JR 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS ; A bank 0 (040H-046H) ; Bank 0 (060H-066H) A ; Non-essential instruction, since EMB = "0"
2. If EMB = "1", exchange bank 0 locations 040H-046H to bank 1 locations 160H-166H: ADATA BDATA EQU EQU SMB LD LD TRANS LD XCHD JR 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS ; A bank 0 (040H-046H) ; Bank 1 (160H-166H) A
3-12
S3C72P9/P72P9 (Preliminary Spec)
ADDRESSING MODES
8-BIT ADDRESSING Table 3-4. 8-Bit Direct and Indirect RAM Addressing Instruction Notation DA Addressing Mode Description Direct: 8-bit address indicated by the RAM address (DA = even number) and memory bank selection EMB Flag Setting 0 Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank 0 Bank 15 Hardware I/O Mapping - All 8-bit addressable peripherals (SMB = 15) -
1 @HL Indirect: the 8-bit address indicated by the memory bank selection and register HL; (the 4-bit L register value must be an even number) 0
000H-FFFH 000H-0FFH
SMB = 0, 1, 2, 3, 4, 15 Bank 0
1
000H-FFFH
SMB = 0, 1, 2, 3, 4, 15
All 8-bit addressable peripherals (SMB = 15)
+ PROGRAMMING TIP -- 8-Bit Addressing Modes
8-Bit Direct Addressing 1. If EMB = "0": ADATA BDATA EQU EQU SMB LD SMB LD LD 2. If EMB = "1": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 EA,P4 0 ADATA,EA BDATA,EA ; (046H) A, (047H) E ; (08EH) A, (08FH) E ; E (P5), A (P4) 46H 8EH 15 EA,P4 0 ADATA,EA BDATA,EA ; (046H) A, (047H) E ; (F8EH) A, (F8FH) E ; Non-essential instruction, since EMB = "0" ; E (P5), A (P4)
3-13
ADDRESSING MODES
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- 8-Bit Addressing Modes (Continued)
8-Bit Indirect Addressing 1. If EMB = "0": ADATA EQU SMB LD LD 2. If EMB = "1": ADATA EQU SMB LD LD 46H 1 HL,#ADATA EA,@HL ; A (146H), E (147H) 46H 1 HL,#ADATA EA,@HL ; A (046H), E (047H) ; Non-essential instruction, since EMB = "0"
3-14
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
4
OVERVIEW
MEMORY MAP
To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current EMB value. I/O MAP FOR HARDWARE REGISTERS Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations F80H-FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map gives you the following information: -- Register address -- Register name (mnemonic for program addressing) -- Bit values (both addressable and non-manipulable) -- Read-only, write-only, or read and write addressability -- 1-bit, 4-bit, or 8-bit data manipulation characteristics
4-1
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
Table 4-1. I/O Map for Memory Bank 15 Memory Bank 15 Address F80H F81H Register SP Bit 3 .3 .7 Bit 2 .2 Bit 1 .1 Bit 0 "0" R/W R/W No Addressing Mode 1-Bit 4-Bit No 8-Bit Yes
.6 .5 .4 Locations F82H-F84H are not mapped. .2 .1 .0 W R .3 No .3 (1) No No No .3 Yes No No No .3 .3 Yes No No No No Yes No Yes No No No Yes No No Yes Yes Yes Yes No Yes No Yes Yes Yes No Yes
F85H F86H F87H F88H F89H F8AH F8BH F8CH F8DH F8EH F90H F91H F92H F94H F95H F96H F97H F98H F99H F9AH FA0H FA1H FA4H FA5H FA6H FA7H
BMOD BCNT WMOD LCNST LMOD LCON TMOD0
.3
.3 .7 .7 .3 .3 .7 .3 .3 "0" TOE1
.2 "0" "0" .2 .2 .6 .2 .2 .6 TOE0
.1 .5 "0" .1 .1 .5 .1 "0" .5 "U"
.0 .4 "0" .0 .0 .4 .0 "0" .4 "0"
W W W W W R/W R W
Locations F8FH is not mapped.
Locations F93H is not mapped. TCNT0 TREF0 WDMOD WDFLAG(2) TMOD1 .3 .7 WDTCF .3 "0" TCNT1A TCNT1B .2 .6 "0" .2 .6 .1 .5 "0" "0" .5 .0 .4 "0" "0" .4 R No No Yes W W
W
Locations F9BH-F9FH are not mapped.
Locations FA2H-FA3H are not mapped.
4-2
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
Table 4-1. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FA8H FA9H FAAH FABH Locations FACH-FAFH are not mapped. FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB7H FB8H FBAH FBBH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H BSC0 BSC1 BSC2 BSC3 Locations FC4H-FCFH are not mapped. IPR PCON IMOD0 IMOD1 IMODK SCMOD PSW IS1 C(3) IME .3 "0" "0" "0" .3 IE4 "0" IEK "0" "0" IE1 "0" IS0 SC2 .2 .2 "0" "0" .2 .2 IRQ4 "0" IRQK "0" "0" IRQ1 "0" EMB SC1 .1 .1 .1 "0" .1 "0" IEB IEW IET1 IET0 IES IE0 IE2 ERB SC0 .0 .0 .0 .0 .0 .0 IRQB IRQW IRQT1 IRQT0 IRQS IRQ0 IRQ2 R/W Yes Yes Yes R/W R W W W W W W R/W R/W Yes No IME No No No No Yes Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Yes No No No No No No No No Yes TREF1B Register TREF1A Bit 3 Bit 2 Bit 1 Bit 0 R/W W No Addressing Mode 1-Bit 4-Bit No 8-Bit Yes
Locations FB9H is not mapped.
4-3
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
Table 4-1. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FD0H FD6H FD7H FD8H FDAH FDCH FDDH FDEH FE0H FE1H FE4H FE5H FE6H FE7H FE8H FE9H FEAH FEBH FECH FEDH FEEH FEFH PMG5 PMG4 PMG3 PMG2 PMG1 PM0.3 "0" PM3.3 "0" PM4.3 PM5.3 PM6.3 PM7.3 PM8.3 PM9.3 PM0.2 PM2.2 PM3.2 "0" PM4.2 PM5.2 PM6.2 PM7.2 PM8.2 PM9.2 PM0.1 PM2.1 PM3.1 "0" PM4.1 PM5.1 PM6.1 PM7.1 PM8.1 PM9.1 PM0.0 PM2.0 PM3.0 "0" PM4.0 PM5.0 PM6.0 PM7.0 PM8.0 PM9.0 Yes Yes Yes Yes W No No Yes SBUF PUMOD2 SMOD PNE2 IMOD2 PUMOD1 Register CLMOD PNE1 Bit 3 .3 .3 "0" .3 "0" PUR3 PUR7 "0" .3 .7 Bit 2 "0" .2 .6 .2 "0" PUR2 PUR6 "0" .2 .6 Bit 1 .1 .1 .5 .1 "0" PUR1 PUR5 PUR9 .1 .5 Bit 0 .0 .0 .4 .0 .0 PUR0 PUR4 PUR8 .0 "0" R/W No No Yes W No .3 Yes No No Yes W W No No No Yes Yes No No No Yes R/W W W No No Addressing Mode 1-Bit 4-Bit Yes No 8-Bit No Yes
Locations FD1H-FD5H are not mapped.
Locations FD9H is not mapped. Locations FDBH is not mapped.
Locations FDFH is not mapped.
Locations FE2H-FE3H are not mapped.
4-4
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
Table 4-1. I/O Map for Memory Bank 15 (Concluded) Memory Bank 15 Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H Register Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Bit 3 .3 .3 "0" .3 .3 .3 / .7 .3 .3 / .7 .3 .3 / .7 Bit 2 .2 .2 .2 .2 .2 .2 / .6 .2 .2 / .6 .2 .2 / .6 Bit 1 .1 .1 .1 .1 .1 .1 / .5 .1 .1 / .5 .1 .1 / .5 Bit 0 .0 .0 .0 .0 .0 .0 / .4 .0 .0 / .4 .0 .0 / .4 R/W R/W R/W R/W R R/W R/W R/W Yes Addressing Mode 1-Bit Yes 4-Bit Yes 8-Bit No
Locations FFAH-FFFH are not mapped.
NOTES: 1. Bit 3 in the WMOD register is read only. 2. F9AH.0, F9AH.1 and F9AH.2 are fixed to "0". 3. The carry flag can be read or written by specific bit manipulation instructions only. 4. The "U" means that the bit is undefined.
4-5
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
REGISTER DESCRIPTIONS
In this section, register descriptions are presented in a consistent format to familiarize you with the memorymapped I/O locations in bank 15 of the RAM. Figure 4-1 describes features of the register description format. Register descriptions are arranged in alphabetical order. Programmers can use this section as a quick-reference source when writing application programs. Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are not included in these descriptions. More detailed information about how these registers are used is included in Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module descriptions.
4-6
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
Register and bit IDs used for bit addressing Register ID Register name
Name of individual bit or related bits Associated hardware module Register location in RAM bank 15
CLMOD - Clock Output Mode Control Register
Bit Identifier RESET Value Read/Write Bit Addressing CLMOD.3 3 .3 0 W 4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FD0H
Enable/Disable Clock Output Control bit 0 0 Disable clock output at the CLO pin Enable clock output at the CLO pin
CLMOD.2
Bit 2 0 Always logic zero
CLMOD.1 -.0
Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock souce fx/4, fx/8, fx/64 (1.05 MHz, 524kHz, or 65.5 kHz), or fxt/4 Select system clock fxx/8 (524 kHz at 4.19 MHz) Select system clock fxx/16 (262 kHz at 4.19 MHz) Select system clock fxx/64 (65.5 kHz at 4.19 MHz)
R = Read-only W = Write-only R/W = Read/write Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit)
Bit value immediately after a RESET
Bit number in MSB to LSB order
Description of the effect of specific bit settings
Bit identifier used for bit addressing
Figure 4-1. Register Description Format
4-7
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
BMOD -- Basic Timer Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing BMOD.3 3 .3 0 W 1/4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
BT
F85H
Basic Timer Restart Bit 1 Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero
BMOD.2 - .0
Input Clock Frequency and Interrupt Interval Time 0 0 1 1 0 1 0 1 0 1 1 1 Input clock frequency: Interrupt interval time (wait time) Input clock frequency: Interrupt interval time (wait time) Input clock frequency: Interrupt interval time (wait time) Input clock frequency: Interrupt interval time (wait time) fxx/ 212 (1.02 kHz) 220/ fxx (250 ms) fxx/ 29 (8.18 kHz) 217/ fxx (31.3 ms) fxx/ 2 (32.7 kHz) 215/ fxx (7.82 ms) fxx/ 25 (131 kHz) 213/ fxx (1.95 ms)
NOTES: 1. When a RESET occurs, the oscillator stabilization wait time is 31.3 ms (217/fxx) at 4.19 MHz. 2. 'fxx' is the system clock rate given a clock frequency of 4.19 MHz.
4-8
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
CLMOD -- Clock Output Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing CLMOD.3 3 .3 0 W 4 2 "0" 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FD0H
Enable/Disable Clock Output Control Bit 0 1 Disable clock output at the CLO pin Enable clock output at the CLO pin
CLMOD.2
Bit 2 0 Always logic zero
CLMOD.1 - .0
Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock source fx/4, fx/8, fx/64 (1.05 MHz, 524 kHz, or 65.5 kHz) or fxt/4 Select system clock fxx/8 (524 kHz) Select system clock fxx/16 (262 kHz) Select system clock fxx/64 (65.5 kHz)
NOTE: 'fxx' is the system clock, given a clock frequency of 4.19 MHz.
4-9
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
IE0, 1, IRQ0, 1 -- INT0, 1 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing IE1 3 IE1 0 R/W 1/4 2 IRQ1 0 R/W 1/4 1 IE0 0 R/W 1/4 0 IRQ0 0 R/W 1/4
CPU
FBEH
INT1 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT1 pin Enable interrupt requests at the INT1 pin
IRQ1
INT1 Interrupt Request Flag - Generate INT1 interrupt (This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin.)
IE0
INT0 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT0 pin Enable interrupt requests at the INT0 pin
IRQ0
INT0 Interrupt Request Flag - Generate INT0 interrupt (This bit is set and cleared automatically by hardware when rising or falling edge detected at INT0 pin.)
4-10
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
IE2, IRQ2 -- INT2 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3 - .2 3 "0" 0 R/W 1/4 Bits 3-2 0 IE2 Always logic zero 2 "0" 0 R/W 1/4 1 IE2 0 R/W 1/4 0 IRQ2 0 R/W 1/4
CPU
FBFH
INT2 Interrupt Enable Flag 0 1 Disable INT2 interrupt requests at the INT2 pin Enable INT2 interrupt requests at the INT2 pin
IRQ2
INT2 Interrupt Request Flag - Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at INT2. Since INT2 is a quasi-interrupt, IRQ2 flag must be cleared by software.)
4-11
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
IE4, IRQ4 -- INT4 Interrupt Enable/Request Flags IEB, IRQB -- INTB Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing IE4 3 IE4 0 R/W 1/4 2 IRQ4 0 R/W 1/4 1 IEB 0 R/W 1/4 0 IRQB 0 R/W 1/4
CPU CPU
FB8H FB8H
INT4 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT4 pin Enable interrupt requests at the INT4 pin
IRQ4
INT4 Interrupt Request Flag - Generate INT4 interrupt (This bit is set and cleared automatically by hardware when rising and falling signal edge detected at INT4 pin.)
IEB
INTB Interrupt Enable Flag 0 1 Disable INTB interrupt requests Enable INTB interrupt requests
IRQB
INTB Interrupt Request Flag - Generate INTB interrupt (This bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
4-12
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
IES, IRQS -- INTS Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3 - .2 3 "0" 0 R/W 1/4 Bits 3-2 0 IES Always logic zero 2 "0" 0 R/W 1/4 1 IES 0 R/W 1/4 0 IRQS 0 R/W 1/4
CPU
FBDH
INTS Interrupt Enable Flag 0 1 Disable INTS interrupt requests Enable INTS interrupt requests
IRQS
INTS Interrupt Request Flag - Generate INTS interrupt (This bit is set and cleared automatically by hardware when serial data transfer completion signal received from serial I/O interface.)
4-13
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
IET0, IRQT0 -- INTT0 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3 - .2 3 "0" 0 R/W 1/4 Bits 3-2 0 IET0 Always logic zero 2 "0" 0 R/W 1/4 1 IET0 0 R/W 1/4 0 IRQT0 0 R/W 1/4
CPU
FBCH
INTT0 Interrupt Enable Flag 0 1 Disable INTT0 interrupt requests Enable INTT0 interrupt requests
IRQT0
INTT0 Interrupt Request Flag - Generate INTT0 interrupt (This bit is set and cleared automatically by hardware when contents of TCNT0 and TREF0 registers match.)
4-14
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
IET1, IRQT1 -- INTT1 Interrupt Enable/Request Flags IEK, IRQK -- INTK Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing IEK 3 IEK 0 R/W 1/4 2 IRQK 0 R/W 1/4 1 IET1 0 R/W 1/4 0 IRQT1 0 R/W 1/4
CPU CPU
FBBH FBBH
INTK Interrupt Enable Flag 0 1 Disable interrupt requests at the K0-K7 pins Enable interrupt requests at the K0-K7 pins
IRQK
INTK Interrupt Request Flag - Generate INTK interrupt (This bit is set and cleared automatically by hardware when rising or falling edge detected at K0-K7 pins.)
IET1
INTT1 Interrupt Enable Flag 0 1 Disable INTT1 interrupt requests Enable INTT1 interrupt requests
IRQT1
INTT1 Interrupt Request Flag - Generate INTT1 interrupt (This bit is set and cleared automatically by hardware when contents of TCNT1 and TREF1 registers match.)
4-15
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
IEW, IRQW -- INTW Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3 - .2 3 "0" 0 R/W 1/4 Bits 3-2 0 IEW Always logic zero 2 "0" 0 R/W 1/4 1 IEW 0 R/W 1/4 0 IRQW 0 R/W 1/4
CPU
FBAH
INTW Interrupt Enable Flag 0 1 Disable INTW interrupt requests Enable INTW interrupt requests
IRQW
INTW Interrupt Request Flag - Generate INTW interrupt (This bit is set when the timer interval is set to 0.5 seconds or 3.91 milliseconds.)
NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.
4-16
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
IMOD0 -- External Interrupt 0 (INT0) Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing IMOD0.3 - .2 3 "0" 0 W 4 Bits 3- 2 0 IMOD0.1 - .0 Always logic zero 2 "0" 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU FB4H
External Interrupt Mode Control Bits 0 0 1 1 0 1 0 1 Interrupt request is triggered by a rising signal edge Interrupt request is triggered by a falling signal edge Interrupt request is triggered by both rising and falling signal edges Interrupt request flag (IRQ0) cannot be set to logic one
4-17
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
IMOD1 -- External Interrupt 1 (INT1) Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing IMOD1.3 - .1 3 "0" 0 W 4 Bits 3-1 0 IMOD1.0 Always logic zero 2 "0" 0 W 4 1 "0" 0 W 4 0 IMOD1.0 0 W 4
CPU FB5H
External Interrupt 1 Edge Detection Control Bit 0 1 Rising edge detection Falling edge detection
4-18
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
IMOD2 -- External Interrupt 2 (INT2) Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing IMOD2.3 - .1 3 "0" 0 W 4 Bits 3-1 0 IMOD2.0 Always logic zero 2 "0" 0 W 4 1 "0" 0 W 4 0 IMOD2.0 0 W 4
CPU
FDAH
External Interrupt 2 Edge Detection Selection Bit 0 1 Interrupt request at INT2 pin trigged by rising edge Interrupt request at INT2 pin trigged by falling edge
4-19
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
IMODK -- External Key Interrupt Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing IMODK.3 3 "0" 0 W 4 Bit 3 0 IMODK.2 Always logic zero 2 0 W 4 1 0 W 4 0 0 W 4 IMODK.2 IMODK.1 IMODK.0
CPU
FB6H
External Key Interrupt Edge Detection Selection Bit 0 1 Falling edge detection Rising edge detection
IMODK.1 - .0
External Key Interrupt Mode Control Bits 0 0 1 1 0 1 0 1 Disable key interrupt Enable edge detection at K0-K3 pins Enable edge detection at K4-K7 pins Enable edge detection at K0-K7 pins
NOTES: 1. To generate a key interrupt, all of the selected pins must be configured to input mode. If any one of the selected pins is configured to output mode, only falling edge can be detected. 2. To generate a key interrupt, all of the selected pins must be at input high state for falling edge detection, or all of the selected pins must be at input low state for rising edge detection. If any one of them or more is at input low state or input high state, the interrupt may be not occurred at falling edge or rising edge. 3. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select edge detection and pins by setting IMODK register.
4-20
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
IPR -- Interrupt Priority Register
Bit Identifier RESET Value Read/Write Bit Addressing IME 3 IME 0 W 1/4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FB2H
Interrupt Master Enable Bit 0 1 Disable all interrupt processing Enable processing for all interrupt service requests
IPR.2 - .0
Interrupt Priority Assignment Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Process all interrupt requests at low priority Only INTB and INT4 interrupts are at high priority Only INT0 interrupt is at high priority Only INT1 interrupt is at high priority Only INTS interrupt is at high priority Only INTT0 interrupt is at high priority Only INTT1 interrupt is at high priority Only INTK interrupt is at high priority
4-21
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
LCNST -- LCD Contrast Control Register
Bit Identifier RESET Value Read/Write Bit Addressing LCNST.7 7 .7 0 W 8 6 "0" 0 W 8 5 "0" 0 W 8 4 "0" 0 W 8 3 .3 0 W 8
LCD
2 .2 0 W 8 1 .1 0 W 8
F8BH, F8AH
0 .0 0 W 8
Enable/Disable LCD Contrast Control Bit 0 1 Disable LCD contrast control Enable LCD contrast control
LCNST.6-.4
Bits 6-4 0 Always logic zero
LCNST.3-.0
LCD Contrast Level Control Bits (16 steps) 0 0 0 * * * 1 0 0 0 * * * 1 0 0 1 * * * 1 0 1 0 * * * 1 1/16 step (The dimmest level) 2/16 step (The dimmest level) 3/16 step (The dimmest level) * * * 16/16 step (The brightest level)
NOTE: VLCD = VDD x (n+17)/32, where n = 0-15.
4-22
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
LCON -- LCD Output Control Register
Bit Identifier RESET Value Read/Write Bit Addressing LCON.3 3 .3 0 W 4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
LCD
F8EH
LCD Duty and Selection Bits 0 1 Select duty by means of LMOD.2 - .0 Select 1/12 duty (COM0 - COM11 is selected)
NOTE: When 1/12 duty is selected, ports 4 should be configured as output mode, and port 5 can be used for Normal I/O port.
LCON.2
LCD Clock Output Disable/Enable Bit 0 1 Disable LCDCK and LCDSY signal outputs. Enable LCDCK and LCDSY signal outputs.
LCON.1 - .0
LCD Output Control Bit 0 0 1 1 0 1 0 1 LCD display off; cut off current to dividing resistor LCD display on; application with internal contrast control LCD display on; application with external contrast control LCD display on*
NOTES: 1. If the external variable resistor for contrast control connected to VLC5, you can select only one contrast control method(External or Internal contrast control). 2. When 1/12 duty is selected by LCON.3, the LCD Clock(LCDCK) Frequency is following.
(LMOD.4 - .3)
LCD Clock (LCDCK) Frequency Selection Bits 0 0 1 1 0 1 0 1 When 1/12 duty: fxx/ 26 (512 Hz) When 1/12 duty: fxx/ 25 (1024 Hz) When 1/12 duty: fxx/ 24 (2048 Hz) When 1/12 duty: fxx/ 23 (4096 Hz)
4-23
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
LMOD -- LCD Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing LMOD.7 - .5 3 .7 0 W 8 2 .6 0 W 8 1 .5 0 W 8 0 .4 0 W 8 3 .3 0 W 8
LCD
2 .2 0 W 8 1 .1 0 W 8
F8DH, F8CH
0 .0 0 W 8
LCD Output Segment and Pin Configuration Bits 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Segments 40-43, 44-47, 48-51 and 52-55 Segments 40-43, 44-47 and 48-51; normal I/O at port 6 Segments 40-43 and 44-47; normal I/O at port 6 and port 7 Segments 40-43; normal I/O at ports 6, 7 and 8 Normal I/O at ports 6, 7, 8 and 9
NOTE: Segment pins that also can used for normal I/O should be configured to output mode when the SEG function is used.
LMOD.4 - .3
LCD Clock (LCDCK) Frequency Selection Bits 0 0 1 1 0 1 0 1 When 1/8 duty: fxx/27 (256 Hz); when 1/12,1/16 duty: fxx/26 (512 Hz) When 1/8 duty: fxx/26 (512 Hz); when 1/12,1/16 duty: fxx/25 (1024 Hz) When 1/8 duty: fxx/25 (1024 Hz); when 1/12,1/16 duty: fxx/24 (2048 Hz) When 1/8 duty: fxx/24 (2048 Hz); when 1/12,1/16 duty: fxx/23 (4096 Hz)
NOTE: LCDCK is supplied only when the watch timer operates. To use the LCD controller, bit 2 in the watch mode register WMOD should be set to 1.
LMOD.2
LCD Duty and Selection Bits 0 1 1/8 duty (COM0-COM7 select) 1/16 duty (COM0-COM15 select)
NOTE: When 1/16 duty is selected, ports 4 and 5 should be configured as output mode; when 1/8 duty is selected, ports 4 and 5 can be used as normal I/O ports.
LMOD.1 - .0
LCD Display Mode Selection Bits 0 0 1 0 1 1 All LCD dots off All LCD dots on Normal display
4-24
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
PCON -- Power Control Register
Bit Identifier RESET Value Read/Write Bit Addressing PCON.3 - .2 3 .3 0 W 4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FB3H
CPU Operating Mode Control Bits 0 0 1 0 1 0 Enable normal CPU operating mode Initiate idle power-down mode Initiate stop power-down mode
PCON.1 - .0
CPU Clock Frequency Selection Bits 0 1 1 0 0 1 If SCMOD.0 = "0", fx/64; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/8; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/4; if SCMOD.0 = "1", fxt/4
NOTE: 'fx' is the main system clock; 'fxt' is the subsystem clock.
4-25
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
PMG1 -- Port I/O Mode Register 1 (Group 1: Ports 0, 2)
Bit Identifier RESET Value Read/Write Bit Addressing .7 7 "0" 0 W 8 Bit 7 0 PM2.2 Always logic zero 6 PM2.2 0 W 8 5 PM2.1 0 W 8 4 PM2.0 0 W 8 3 PM0.3 0 W 8
I/O
2 PM0.2 0 W 8 1
FE7H, FE6H
0 PM0.0 0 W 8
PM0.1 0 W 8
P2.2 I/O Mode Selection Flag 0 1 Set P2.2 to input mode Set P2.2 to output mode
PM2.1
P2.1 I/O Mode Selection Flag 0 1 Set P2.1 to input mode Set P2.1 to output mode
PM2.0
P2.0 I/O Mode Selection Flag 0 1 Set P2.0 to input mode Set P2.0 to output mode
PM0.3
P0.3 I/O Mode Selection Flag 0 1 Set P0.3 to input mode Set P0.3 to output mode
PM0.2
P0.2 I/O Mode Selection Flag 0 1 Set P0.2 to input mode Set P0.2 to output mode
PM0.1
P0.1 I/O Mode Selection Flag 0 1 Set P0.1 to input mode Set P0.1 to output mode
PM0.0
P0.0 I/O Mode Selection Flag 0 1 Set P0.0 to input mode Set P0.0 to output mode
4-26
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
PMG2 -- Port I/O Mode Register 2 (Group 2: Port 3)
Bit Identifier RESET Value Read/Write Bit Addressing .7 - .4 7 "0" 0 W 8 Bits 7 - 4 0 PM3.3 Always logic zero 6 "0" 0 W 8 5 "0" 0 W 8 4 "0" 0 W 8 3 PM3.3 0 W 8
I/O
2 PM3.2 0 W 8 1
FE9H, FE8H
0 PM3.0 0 W 8
PM3.1 0 W 8
P3.3 I/O Mode Selection Flag 0 1 Set P3.3 to input mode Set P3.3 to output mode
PM3.2
P3.2 I/O Mode Selection Flag 0 1 Set P3.2 to input mode Set P3.2 to output mode
PM3.1
P3.1 I/O Mode Selection Flag 0 1 Set P3.1 to input mode Set P3.1 to output mode
PM3.0
P3.0 I/O Mode Selection Flag 0 1 Set P3.0 to input mode Set P3.0 to output mode
4-27
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
PMG3 -- Port I/O Mode Register 3 (Group 3: Ports 4, 5)
Bit Identifier RESET Value Read/Write Bit Addressing PM5.3 7 PM5.3 0 W 8 6 PM5.2 0 W 8 5 PM5.1 0 W 8 4 PM5.0 0 W 8 3 PM4.3 0 W 8
I/O
2 PM4.2 0 W 8
FEBH, FEAH
1 PM4.1 0 W 8 0 PM4.0 0 W 8
P5.3 I/O Mode Selection Flag 0 Set P5.3 to input mode 1 Set P5.3 to output mode P5.2 I/O Mode Selection Flag 0 Set P5.2 to input mode 1 Set P5.2 to output mode P5.1 I/O Mode Selection Flag 0 Set P5.1 to input mode 1 Set P5.1 to output mode P5.0 I/O Mode Selection Flag 0 Set P5.0 to input mode 1 Set P5.0 to output mode P4.3 I/O Mode Selection Flag 0 Set P4.3 to input mode 1 Set P4.3 to output mode P4.2 I/O Mode Selection Flag 0 Set P4.2 to input mode 1 Set P4.2 to output mode P4.1 I/O Mode Selection Flag 0 Set P4.1 to input mode 1 Set P4.1 to output mode P4.0 I/O Mode Selection Flag 0 Set P4.0 to input mode 1 Set P4.0 to output mode
PM5.2
PM5.1
PM5.0
PM4.3
PM4.2
PM4.1
PM4.0
4-28
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
PMG4 -- Port I/O Mode Register 4 (Group 4: Ports 6, 7)
Bit Identifier RESET Value Read/Write Bit Addressing PM7.3 7 PM7.3 0 W 8 6 PM7.2 0 W 8 5 PM7.1 0 W 8 4 PM7.0 0 W 8 3 PM6.3 0 W 8
I/O
2 PM6.2 0 W 8
FEDH, FECH
1 PM6.1 0 W 8 0 PM6.0 0 W 8
P7.3 I/O Mode Selection Flag 0 Set P7.3 to input mode 1 Set P7.3 to output mode P7.2 I/O Mode Selection Flag 0 Set P7.2 to input mode 1 Set P7.2 to output mode P7.1 I/O Mode Selection Flag 0 Set P7.1 to input mode 1 Set P7.1 to output mode P7.0 I/O Mode Selection Flag 0 Set P7.0 to input mode 1 Set P7.0 to output mode P6.3 I/O Mode Selection Flag 0 Set P6.3 to input mode 1 Set P6.3 to output mode P6.2 I/O Mode Selection Flag 0 Set P6.2 to input mode 1 Set P6.2 to output mode P6.1 I/O Mode Selection Flag 0 Set P6.1 to input mode 1 Set P6.1 to output mode P6.0 I/O Mode Selection Flag 0 Set P6.0 to input mode 1 Set P6.0 to output mode
PM7.2
PM7.1
PM7.0
PM6.3
PM6.2
PM6.1
PM6.0
4-29
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
PMG5 -- Port I/O Mode Register 5 (Group 5: Ports 8, 9)
Bit Identifier RESET Value Read/Write Bit Addressing PM9.3 7 PM9.3 0 W 8 6 PM9.2 0 W 8 5 PM9.1 0 W 8 4 PM9.0 0 W 8 3 PM8.3 0 W 8
I/O
2 PM8.2 0 W 8
FEFH, FEEH
1 PM8.1 0 W 8 0 PM8.0 0 W 8
P9.3 I/O Mode Selection Flag 0 Set P9.3 to input mode 1 Set P9.3 to output mode P9.2 I/O Mode Selection Flag 0 Set P9.2 to input mode 1 Set P9.2 to output mode P9.1 I/O Mode Selection Flag 0 Set P9.1 to input mode 1 Set P9.1 to output mode P9.0 I/O Mode Selection Flag 0 Set P9.0 to input mode 1 Set P9.0 to output mode P8.3 I/O Mode Selection Flag 0 Set P8.3 to input mode 1 Set P8.3 to output mode P8.2 I/O Mode Selection Flag 0 Set P8.2 to input mode 1 Set P8.2 to output mode P8.1 I/O Mode Selection Flag 0 Set P8.1 to input mode 1 Set P8.1 to output mode P8.0 I/O Mode Selection Flag 0 Set P8.0 to input mode 1 Set P8.0 to output mode
PM9.2
PM9.1
PM9.0
PM8.3
PM8.2
PM8.1
PM8.0
4-30
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
PNE1 -- N-Channel Open-Drain Mode Register 1
Bit Identifier RESET Value Read/Write Bit Addressing .7 7 "0" 0 W 8 6 PNE1.6 0 W 8 5 PNE1.5 0 W 8 4 PNE1.4 0 W 8 3 PNE1.3 0 W 8
I/O
2 PNE1.2 0 W 8
FD7H, FD6H
1 PNE1.1 0 W 8 0 PNE1.0 0 W 8
Bit 7 0 Always logic 0 P2.2 N-Channel Open-Drain Configurable Bit 0 Configure P2.2 as a push-pull 1 Configure P2.2 as a n-channel open-drain P2.1 N-Channel Open-Drain Configurable Bit 0 Configure P2.1 as a push-pull 1 Configure P2.1 as a n-channel open-drain P2.0 N-Channel Open-Drain Configurable Bit 0 Configure P2.0 as a push-pull 1 Configure P2.0 as a n-channel open-drain P0.3 N-Channel Open-Drain Configurable Bit 0 Configure P0.3 as a push-pull 1 Configure P0.3 as a n-channel open-drain P0.2 N-Channel Open-Drain Configurable Bit 0 Configure P0.2 as a push-pull 1 Configure P0.2 as a n-channel open-drain P0.1 N-Channel Open-Drain Configurable Bit 0 Configure P0.1 as a push-pull 1 Configure P0.1 as a n-channel open-drain P0.0 N-Channel Open-Drain Configurable Bit 0 Configure P0.0 as a push-pull 1 Configure P0.0 as a n-channel open-drain
PNE1.6
PNE1.5
PNE1.4
PNE1.3
PNE1.2
PNE1.1
PNE1.0
4-31
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
PNE2 -- N-Channel Open-Drain Mode Register 2
Bit Identifier RESET Value Read/Write Bit Addressing PNE2.3 3 PNE2.3 0 W 4 2 PNE2.2 0 W 4 1 PNE2.1 0 W 4 0 PNE2.0 0 W 4
I/O
FD8H
P3.3 N-Channel Open-Drain Configurable Bit 0 1 Configure P3.3 as a push-pull Configure P3.3 as a n-channel open-drain
PNE2.2
P3.2 N-Channel Open-Drain Configurable Bit 0 1 Configure P3.2 as a push-pull Configure P3.2 as a n-channel open-drain
PNE2.1
P3.1 N-Channel Open-Drain Configurable Bit 0 1 Configure P3.1 as a push-pull Configure P3.1 as a n-channel open-drain
PNE2.0
P3.0 N-Channel Open-Drain Configurable Bit 0 1 Configure P3.0 as a push-pull Configure P3.0 as a n-channel open-drain
4-32
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
PSW -- Program Status Word
Bit Identifier RESET Value Read/Write Bit Addressing C 7 C
(1)
CPU
6 5 SC1 0 R 8 4 SC0 0 R 8 3 IS1 0 R/W 1/4/8 2 IS0 0 R/W 1/4/8 1
FB1H, FB0H
0 ERB 0 R/W 1/4/8
SC2 0 R 8
EMB 0 R/W 1/4/8
R/W
(2)
Carry Flag 0 1 No overflow or borrow condition exists An overflow or borrow condition does exist
SC2 - SC0
Skip Condition Flags 0 1 No skip condition exists; no direct manipulation of these bits is allowed A skip condition exists; no direct manipulation of these bits is allowed
IS1, IS0
Interrupt Status Flags 0 0 1 1 0 1 0 1 Service all interrupt requests Service only the high-priority interrupt(s) as determined in the interrupt priority register (IPR) Do not service any more interrupt requests Undefined
EMB
Enable Data Memory Bank Flag 0 1 Restrict program access to data memory to bank 15 (F80H-FFFH) and to the locations 000H-07FH in the bank 0 only Enable full access to data memory banks 0, 1, 2, 3, 4 and 15
ERB
Enable Register Bank Flag 0 1 Select register bank 0 as working register area Select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (SRB) instruction operand
NOTES: 1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during power-down mode (IDLE or STOP), the current value of the carry flag is retained. 2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for detailed information.
4-33
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
PUMOD1 -- Pull-up Resistor Mode Register 1 I/O
Bit Identifier RESET Value Read/Write Bit Addressing PUR7 7 PUR7 0 W 8 6 PUR6 0 W 8 5 PUR5 0 W 8 4 PUR4 0 W 8
FDDH, FDCH
3 PUR3 0 W 8 2 PUR2 0 W 8 1 PUR1 0 W 8 0 PUR0 0 W 8
Connect/Disconnect Port 7 Pull-up Resistor Control Bit 0 1 Disconnect port 7 pull-up resistor Connect port 7 pull-up resistor
PUR6
Connect/Disconnect Port 6 Pull-up Resistor Control Bit 0 1 Disconnect port 6 pull-up resistor Connect port 6 pull-up resistor
PUR5
Connect/Disconnect Port 5 Pull-up Resistor Control Bit 0 1 Disconnect port 5 pull-up resistor Connect port 5 pull-up resistor
PUR4
Connect/Disconnect Port 4 Pull-up Resistor Control Bit 0 1 Disconnect port 4 pull-up resistor Connect port 4 pull-up resistor
PUR3
Connect/Disconnect Port 3 Pull-up Resistor Control Bit 0 1 Disconnect port 3 pull-up resistor Connect port 3 pull-up resistor
PUR2
Connect/Disconnect Port 2 Pull-up Resistor Control Bit 0 1 Disconnect port 2 pull-up resistor Connect port 2 pull-up resistor
PUR1
Connect/Disconnect Port 1 Pull-up Resistor Control Bit 0 1 Disconnect port 1 pull-up resistor Connect port 1 pull-up resistor
PUR0
Connect/Disconnect Port 0 Pull-up Resistor Control Bit 0 1 Disconnect port 0 pull-up resistor Connect port 0 pull-up resistor
4-34
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
PUMOD2 -- Pull-up Resistor Mode Register 2
Bit Identifier RESET Value Read/Write Bit Addressing .3 - .2 3 "0" 0 W 4 Bits 3 - 2 0 PUR9 Always cleared to logic zero 2 "0" 0 W 4 1 PUR9 0 W 4 0 PUR8 0 W 4
I/O
FDEH
Connect/Disconnect Port 9 Pull-up Resistor Control Bit 0 1 Disconnect port 9 pull-up resistor Connect port 9 pull-up resistor
PUR8
Connect/Disconnect Port 8 Pull-up Resistor Control Bit 0 1 Disconnect port 8 pull-up resistor Connect port 8 pull-up resistor
4-35
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
SCMOD -- System Clock Mode Control Register
Bit Identifier RESET Value Read/Write Bit Addressing SCMOD.3 3 .3 0 W 1 Bit 3 0 1 SCMOD.2 Bit 2 0 1 SCMOD.1 Bit 1 0 SCMOD.0 Bit 0 0 1 Select main system clock Select sub system clock Always logic zero Enable sub system clock Disable sub system clock Enable main system clock Disable main system clock 2 .2 0 W 1 1 "0" 0 W 1 0 .0 0 W 1
CPU
FB7H
NOTES: 1. Sub-oscillation goes into stop mode only by SCMOD.2. PCON which revokes stop mode cannot stop the suboscillation. 2. You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed): Main operation sub-operation sub-idle (LCD on, after a few minutes later without any external input) suboperation main operation SCMOD.2 = 1 main stop mode (LCD off). 3. SCMOD bits 3-0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions.
4-36
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
SMOD -- Serial I/O Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing SMOD.7 - .5 7 .7 0 W 8 6 .6 0 W 8 5 .5 0 W 8 4 "0" 0 W 8 3 .3 0 W 1/8
SIO
2 .2 0 W 8 1 .1 0 W 8
FE1H, FE0H
0 .0 0 W 8
Serial I/O Clock Selection and SBUF R/W Status Control Bits 0 0 0 Use an external clock at the SCK pin; 0 0 1 1 0 1 0 1 1 x 0 1
Enable SBUF when SIO operation is halted or when SCK goes high Use the TOL0 clock from timer/counter 0; Enable SBUF when SIO operation is halted or when SCK goes high Use the selected CPU clock (fxx/4, 8, or 64; 'fxx' is the system clock) then, enable SBUF read/write operation. 'x' means 'don't care.' 4.09 kHz clock (fxx/210) 262 kHz clock (fxx/24); Note: You cannot select a fxx/24 clock frequency if you have selected a CPU clock of fxx/64
NOTE: All kHz frequency ratings assume a system clock of 4.19 MHz.
SMOD.4
Bit 4 0 Always logic zero Initiate Serial I/O Operation Bit 1 Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial transmission. When SIO transmission starts, this bit is cleared by hardware to logic zero Enable/Disable SIO Data Shifter and Clock Counter Bit 0 Disable the data shifter and clock counter; the contents of IRQS flag is retained when serial transmission is completed 1 Enable the data shifter and clock counter; The IRQS flag is set to logic one when serial transmission is completed Serial I/O Transmission Mode Selection Bit 0 Receive-only mode 1 Transmit-and-receive mode LSB/MSB Transmission Mode Selection Bit 0 Transmit the most significant bit (MSB) first 1 Transmit the least significant bit (LSB) first
SMOD.3
SMOD.2
SMOD.1
SMOD.0
4-37
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
TMOD0 -- Timer/Counter 0 Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing TMOD0.7 7 "0" 0 W 8 Bit 7 0 TMOD0.6 - .4 Always logic zero 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 W 1/8
T/C0
2 .2 0 W 8 1 "0" 0 W 8
F91H, F90H
0 "0" 0 W 8
Timer/Counter 0 Input Clock Selection Bits 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 External clock input at TCL0 pin on rising edge External clock input at TCL0 pin on falling edge fxx/210 (4.09 kHz) fxx/26 (65.5 kHz) fxx/24 (262 kHz) fxx (4.19 MHz)
NOTE: "fxx" is selected system clock of 4.19 MHz
TMOD0.3
Clear Counter and Resume Counting Control Bit 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is cleared automatically when counting starts.)
TMOD0.2
Enable/Disable Timer/Counter 0 Bit 0 1 Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0
TMOD0.1
Bit 1 0 Always logic zero
TMOD0.0
Bit 0 0 Always logic zero
4-38
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
TMOD1 -- Timer/Counter 1 Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing TMOD1.7 3 "0" 0 W 8 Bit 7 0 TMOD1.6 - .4 Always logic zero 2 .6 0 W 8 1 .5 0 W 8 0 .4 0 W 8 3 .3 0 W 1/8
T/C
2 .2 0 W 8 1
FA1H, FA0H
0 "0" 0 W 8
"0" 0 W 8
Timer/Counter 1 Input Clock Selection Bit 0 0 1 1 1 1
NOTE:
0 0 0 0 1 1
0 1 0 1 0 1
External clock input at TCL1 pin on rising edge External clock input at TCL1 pin on falling edge fxx/210 (4.09 kHz) fxx/28 (16.4 kHz) fxx/26 (65.5 kHz) fxx/24 (262 kHz)
"fxx" is selected system clock of 4.19 MHz
TMOD1.3
Clear Counter and Resume Counting Control Bit 1 Clear TCNT1, IRQT1, and TOL1 and resume counting immediately (This bit is cleared automatically when counting starts.)
TMOD1.2
Enable/Disable Timer/Counter 1 Bit 0 1 Disable timer/counter 1; retain TCNT1 contents Enable timer/counter 1
TMOD1.1
Bit 1 0 Always logic zero
TMOD1.0
Bit 0 0 Always logic zero
4-39
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
TOE -- Timer Output Enable Flag Register
Bit Identifier RESET Value Read/Write Bit Addressing TOE1 3 TOE1 0 R/W 1/4 2 TOE0 0 R/W 1/4 1 "U" U R/W 1/4 0 "0" 0 R/W 1/4
T/C
F92H
Timer/Counter 1 Output Enable Flag 0 1 Disable timer/counter 1 clock output at the TCLO1 pin Enable timer/counter 1 clock output at the TCLO1 pin
TOE0
Timer/Counter 0 Output Enable Flag 0 1 Disable timer/counter 0 clock output at the TCLO0 pin Enable timer/counter 0 clock output at the TCLO0 pin
.1
Bits 1 U This bit is undefined
.0
Bits 0 0 Always logic zero
4-40
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
WDFLAG -- Watch-Dog Timer's Counter Clear Flag
Bit Identifier RESET Value Read/Write Bit Addressing 3 WDTCF 0 W 1/4 2 "0" 0 W 1/4 1 "0" 0 W 1/4 0 "0" 0 W 1/4
WT
F9AH.3
WDTCF
Watch-dog Timer's Counter Clear Bit 0 1 - Clear the WDT's counter to zero and restart the WDT's counter
WDFLAG.2 - .0
Bit2 - 0 0 Always logic zero
4-41
MEMORY MAP
S3C72P9/P72P9 (Preliminary Spec)
WDMOD -- Watch-Dog Timer Mode Control Register
Bit Identifier RESET Value Read/Write Bit Addressing WMOD.7 - .0 3 .7 1 W 8 2 .6 0 W 8 1 .5 1 W 8 0 .4 0 W 8 3 .3
0
WT
2 .2 1 W 8 1 .1 0 W 8
F99H, F98H
0 .0 1 W 8
W 8
Watch-Dog Timer Enable/Disable Control 0 1 0 1 1 0 1 0 Disable watch-dog timer function Enable watch-dog timer function Other Values
4-42
S3C72P9/P72P9 (Preliminary Spec)
MEMORY MAP
WMOD -- Watch Timer Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing WMOD.7 7 .7 0 W 8 6 "0" 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3
(note)
WT
2 .2 0 W 8 1 .1 0 W 8
F89H, F88H
0 .0 0 W 8
R 1
Enable/Disable Buzzer Output Bit 0 1 Disable buzzer (BUZ) signal output at the BUZ pin Enable buzzer (BUZ) signal output at the BUZ pin
WMOD.6
Bit 6 0 Always logic zero
WMOD.5 - .4
Output Buzzer Frequency Selection Bits 0 0 1 1 0 1 0 1 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output
WMOD.3
XTIN Input Level Control Bit 0 1 Input level to XTIN pin is low; 1-bit read-only addressable for tests Input level to XTIN pin is high; 1-bit read-only addressable for tests
WMOD.2
Enable/Disable Watch Timer Bit 0 1 Disable watch timer and clear frequency dividing circuits Enable watch timer
WMOD.1
Watch Timer Speed Control Bit 0 1 Normal speed; set IRQW to 0.5 seconds High-speed operation; set IRQW to 3.91 ms
WMOD.0
Watch Timer Clock Selection Bit 0 1 Select main system clock (fx)/128 as the watch timer clock Select a subsystem clock as the watch timer clock
NOTE: RESET sets WMOD.3 to the current input level of the subsystem clock, XTIN. If the input level is high, WMOD.3 is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register.
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S3C72P9/P72P9 (Preliminary Spec)
OSCILLATOR CIRCUITS
6
OVERVIEW
-- -- -- -- -- --
OSCILLATOR CIRCUITS
The S3C72P9 microcontroller have two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. Specifically, a clock pulse is required by the following peripheral modules: LCD controller Basic timer Timer/counters 0 and 1 Watch timer Serial I/O interface Clock output circuit
CPU Clock Notation In this document, the following notation is used for descriptions of the CPU clock: fx fxt fxx Main system clock Subsystem clock Selected system clock
Clock Control Registers When the system clock mode register, SCMOD, and the power control register, PCON, are both cleared to zero after RESET, the normal CPU operating mode is enabled, a main system clock is selected as fx/64, and main system clock oscillation is initiated. The PCON is used to select normal CPU operating mode or one of two power down mode-stop or idle. Bits 3 and 2 of the PCON register can be manipulated by STOP or IDLE instruction to engage stop or idle power down mode. The SCMOD, lets you select the main system clock (fx) or a subsystem clock (fxt) as the CPU clock and start (or stop) main/sub system clock oscillation. The resulting clock source, either main system clock or subsystem clock, is referred to the selected system clock (fxx). The main system clock is selected and oscillation started when all SCMOD bits are cleared to "0". By setting SCMOD.3, SCMOD.2 and SCMOD.0 to different values, you can select a subsystem clock source and start or stop main/sub system clock oscillation. To stop main system clock oscillation, you must use the STOP instruction (assuming the main system clock is selected) or manipulate SCMOD.3 to (assuming the sub system clock is selected). The main system clock frequencies can be divided by 4, 8, or 64 and a subsystem clock frequencies can only be divided by 4. By manipulating PCON bits 1 and 0, you select one of the following frequencies as the CPU clock. fx/4, fxt/4, fx/8, fx/64
6-1
OSCILLATOR CIRCUITS
S3C72P9/P72P9 (Preliminary Spec)
Using a Subsystem Clock If a subsystem clock is being used as the selected system clock, the idle power-down mode can be initiated by executing an IDLE instruction. The watch timer, buzzer and LCD display operate normally with a subsystem clock source, since they operate at very low speed (as low as 122 s at 32.768 kHz) and with very low power consumption.
Main-system Oscillator Circuit
fx
fxt
Sub-system Oscillator Circuit Oscillator Stop
Watch Timer LCD Controller
Selector XIN XOUT fxx
XTIN
XTOUT
Oscillator Stop
1/1-1/4096 Frequency Dividing Circuit 1/2 1/16 Basic Timer Timer/Counter Watch Timer LCD Controller Clock Output Circuit
SCMOD.3 Selector SCMOD.0 SCMOD.2 fx/1, 2, 16 fxt Selector
PCON.0 PCON.1 Idle Stop PCON.2 PCON.3 Oscillator Control Circuit
CPU stop signal (IDLE mode) Wait release signal
1/4 CPU Clock
Internal RESET signal Power down release signal
PCON.3, .2 clear
fx: Main-system clock fxt: Sub-system clock fxx: System clock
Figure 6-1. Clock Circuit Diagram
6-2
S3C72P9/P72P9 (Preliminary Spec)
OSCILLATOR CIRCUITS
MAIN SYSTEM OSCILLATOR CIRCUITS
SUB SYSTEM OSCILLATOR CIRCUITS
XIN
XTIN
XOUT 32.768 kHz
XTOUT
Figure 6-2. Crystal/Ceramic Oscillator (fx)
Figure 6-5. Crystal/Ceramic Oscillator (fxt)
XIN External Clock XOUT
XTIN
XTOUT
Figure 6-3. External Oscillator (fx)
Figure 6-6. External Oscillator (fxt)
XIN R XOUT
Figure 6-4. RC Oscillator (fx)
6-3
OSCILLATOR CIRCUITS
S3C72P9/P72P9 (Preliminary Spec)
POWER CONTROL REGISTER (PCON) The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control CPU operating and power-down modes. PCON can be addressed directly by 4-bit write instructions or indirectly by the instructions IDLE and STOP. FB3H PCON.3 PCON.2 PCON.1 PCON.0
PCON bits 3 and 2 are addressed by the STOP and IDLE instructions, respectively, to engage the idle and stop power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency. There are two basic choices: -- Main system clock (fx) or subsystem clock (fxt); -- Divided fx/4, 8, 64 or fxt/4 clock frequency. PCON.1 and PCON.0 settings are also connected with the system clock mode control register, SCMOD. If SCMOD.0 = "0" the main system clock is always selected by the PCON.1 and PCON.0 setting; if SCMOD.0 = "1" the subsystem clock is selected. RESET sets PCON register values (and SCMOD) to logic zero: SCMOD.3 and SCMOD.0 select the main system clock (fx) and start clock oscillation; PCON.1 and PCON.0 divide the selected fx frequency by 64, and PCON.3 and PCON.2 enable normal CPU operating mode. Table 6-1. Power Control Register (PCON) Organization PCON Bit Settings PCON.3 0 0 1 PCON.2 0 1 0 Normal CPU operating mode Idle power-down mode Stop power-down mode Resulting CPU Clock Frequency If SCMOD.0 = "0" fx/64 fx/8 fx/4 If SCMOD.0 = "1" fxt/4 Resulting CPU Operating Mode
PCON Bit Settings PCON.1 0 1 1 PCON.0 0 0 1
+ PROGRAMMING TIP -- Setting the CPU Clock
To set the CPU clock to 0.95 s at 4.19 MHz: BITS SMB LD LD EMB 15 A,#3H PCON,A
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S3C72P9/P72P9 (Preliminary Spec)
OSCILLATOR CIRCUITS
INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on whether the main system clock (fx) or a subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). Table 6-2 shows corresponding cycle times in microseconds. Table 6-2. Instruction Cycle Times for CPU Clock Rates Selected CPU Clock fx/64 fx/8 fx/4 fxt/4 Resulting Frequency 65.5 kHz 524.0 kHz 1.05 MHz 8.19 kHz fxt = 32.768 kHz fx = 4.19 MHz Oscillation Source Cycle Time (sec) 15.3 1.91 0.95 122.0
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OSCILLATOR CIRCUITS
S3C72P9/P72P9 (Preliminary Spec)
SYSTEM CLOCK MODE REGISTER (SCMOD) The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control main and sub-system clock oscillation. The SCMOD is mapped to the RAM address FB7H. The main clock oscillation is stopped by setting SCMOD.3 when the clock source is subsystem clock and subsystem clock can be stopped by setting SCMOD.2 when the clock source is main system clock. SCMOD.0, SCMOD.3 cannot be simultaneously modified. The subsystem clock is stopped only by setting SCMOD.2, and PCON which revokes stop mode cannot stop the subsystem clock. The stop of subsystem clock is released by RESET when the selected system clock is main system clock or subsystem clock and is released by setting SCMOD.2 when the selected system clock is main system clock. RESET clears all SCMOD values to logic zero, selecting the main system clock (fx) as the CPU clock and starting clock oscillation. The reset value of the SCMOD is "0" SCMOD.0, SCMOD.2, and SCMOD.3 bits can be manipulated by 1-bit write instructions (In other words, SCMOD.0, SCMOD.2, and SCMOD.3 cannot be modified simultaneously by a 4-bit write). Bit 1 is always logic zero. FB7H SCMOD.3 SCMOD.2 "0" SCMOD.0
A subsystem clock (fxt) can be selected as the system clock by manipulating the SCMOD.3 and SCMOD.0 bit settings. If SCMOD.3 = "0" and SCMOD.0 = "1", the subsystem clock is selected and main system clock oscillation continues. If SCMOD.3 = "1" and SCMOD.0 = "1", fxt is selected, but main system clock oscillation stops. Even if you have selected fx as the CPU clock, setting SCMOD.3 to "1" will stop main system clock oscillation, and malfunction may be occured. To operate safely, main system clock should be stopped by a stop instruction is main system clock mode. Table 6-3. System Clock Mode Register (SCMOD) Organization SCMOD Register Bit Settings SCMOD.3 0 0 1 SCMOD.2 0 1
NOTE:
Resulting Clock Selection CPU Clock Source fx fxt fxt Sub-oscillation on/off Enable sub system clock Disable sub system clock fx Oscillation On On Off
SCMOD.0 0 1 1
You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed): Main operation sub-operation sub-idle (LCD on, after a few minutes later without any external input) sub-operation main operation SCMOD.2 = 1 main stop mode (LCD off).
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S3C72P9/P72P9 (Preliminary Spec)
OSCILLATOR CIRCUITS
Table 6-4. Main/Sub Oscillation Stop Mode Mode Main Oscillation STOP Mode Condition Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Method to issue Osc Stop STOP instruction: Main oscillator stops. CPU is in idle mode. Sub oscillator still runs (stops). Osc Stop Release Source (2) Interrupt and RESET: After releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. And then the CPU operates. Oscillation stabilization time is 1/ {256 x BT clock (fx)}. RESET: Interrupt can't start the main oscillation. Therefore, the CPU operation can never be restarted. BT overflow, interrupt, and RESET: After the overflow of basic timer [1/ {256 x BT clock (fxt)}], CPU operation and main oscillation automatically start. Set SCMOD.3 to "0" or RESET
When SCMOD.3 is set to "1" (1), main oscillator stops, halting the CPU operation. Sub oscillator still runs (stops). Main oscillator runs. Sub oscillator runs. System clock is the sub oscillation clock. STOP instruction: Main oscillator stops. CPU is in idle mode. Sub oscillator still runs (stops). Sub oscillator still runs. When SCMOD.3 is set to "1", main oscillator stops. The CPU, however, would still operate. Sub oscillator still runs. Sub Oscillation STOP Mode Main oscillator runs. Sub oscillator runs. System clock is the main oscillation clock. Main oscillator runs (stops). Sub oscillator runs. System clock is the sub oscillation clock. When SCMOD.2 to "1", sub oscillator stops, while main oscillator and the CPU would still operate. When SCMOD.2 to "1", sub oscillator stops, halting the CPU operation. Main oscillator still runs (stops).
Set SCMOD.2 to "0" or RESET
RESET
NOTES: 1. This mode must not be used. 2. Oscillation stabilization time by interrupt is 1/ (256 x BT clocks). Oscillation stabilization time by a reset is 31.3ms at 4.19Mhz, main oscillation clock.
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OSCILLATOR CIRCUITS
S3C72P9/P72P9 (Preliminary Spec)
SWITCHING THE CPU CLOCK Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD, determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies. SCMOD.3, SCMOD.2, and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, or 64,or fxt clock by 4. NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications -- the previously selected clock continues to run for a certain number of machine cycles. For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you first need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation to continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After this time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1". This same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear SCMOD.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all SCMOD values to logic zero. Following a RESET, CPU operation starts with the lowest main system clock frequency of 15.3 s at 4.19 MHz after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-4 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect. Table 6-5. Elapsed Machine Cycles During CPU Clock Switch
AFTER BEFORE PCON.1 = 0 PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 SCMOD.0 = 1 PCON.1 = 0 PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 SCMOD.0 = 1
N/A
1 MACHINE CYCLE
1 MACHINE CYCLE
N/A
8 MACHINE CYCLES
N/A
1 MACHINE CYCLES
N/A
16 MACHINE CYCLES
1 MACHINE CYCLES
N/A
fx / 4fxt
N/A
N/A
1MACHINE CYCLES
N/A
NOTES: 1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered. 2. Since the XIN input is connected internally to VSS to avoid current leakage due to the crystal oscillator in stop mode, do 3. 4. 5. not set SCMOD.3 to "1" or do not use stop instruction when an external clock is used as the main system clock. When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in Table 6-4. 'N/A' means 'not available'. fx: Main-system clock, fxt: Sub-system clock. When fx is 4.19 MHz, and fxt is 32.768 kHz.
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S3C72P9/P72P9 (Preliminary Spec)
OSCILLATOR CIRCUITS
+ PROGRAMMING TIP -- Switching Between Main System and Subsystem Clock
1. Switch from the main system clock to the subsystem clock: MA2SUB BITS CALL BITS RET DLY80 DEL1 LD NOP NOP DECS JR RET 2. Switch from the subsystem clock to the main system clock: SUB2MA BITR CALL CALL BITR RET SCMOD.3 DLY80 DLY80 SCMOD.0 ; Switch to main system clock ; Start main system clock oscillation ; Delay 160 machine cycles A DEL1 A,#0FH SCMOD.0 DLY80 SCMOD.3 ; Switches to subsystem clock ; Delay 80 machine cycles ; Stop the main system clock
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OSCILLATOR CIRCUITS
S3C72P9/P72P9 (Preliminary Spec)
CLOCK OUTPUT MODE REGISTER (CLMOD) The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions only. FD0H CLMOD.3 "0" CLMOD.1 CLMOD.0
RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without initiating clock oscillation), and disables clock output. CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64. Table 6-6. Clock Output Mode Register (CLMOD) Organization CLMOD Bit Settings CLMOD.1 0 0 1 1 CLMOD.3 0 1 CLMOD.0 0 1 0 1 fxx/8 fxx/16 fxx/64 Clock Source CPU clock (fx/4, fx/8, fx/64, fxt/4) 524 kHz 262 kHz 65.5 kHz Result of CLMOD.3 Setting Disable clock output at the CLO pin Enable clock output at the CLO pin Resulting Clock Output Frequency 1.05 MHz, 524 kHz, 65.5 kHz, 8.2 kHz
NOTE: Frequencies assume that fxx, fx = 4.19 MHz and fxt = 32.768 kHz.
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S3C72P9/P72P9 (Preliminary Spec)
OSCILLATOR CIRCUITS
CLOCK OUTPUT CIRCUIT The clock output circuit, used to output clock pulses to the CLO pin, has the following components: -- 4-bit clock output mode register (CLMOD) -- Clock selector -- Output latch -- Port mode flag -- CLO output pin (P2.0)
CLMOD.3 CLO CLMOD.2 4 CLMOD.1 CLMOD.0 Clock Selector P1.2 Output Latch PM 2
Clocks (fxx/8, fxx/16, fxx/64, CPU clock)
Figure 6-7. CLO Output Pin Circuit Diagram
CLOCK OUTPUT PROCEDURE The procedure for outputting clock pulses to the CLO pin may be summarized as follows: 1. Disable clock output by clearing CLMOD.3 to logic zero. 2. Set the clock output frequency (CLMOD.1, CLMOD.0). 3. Load a "0" to the output latch of the CLO pin (P2.0). 4. Set the P2.0 mode flag (PM2.0) to output mode. 5. Enable clock output by setting CLMOD.3 to logic one.
+ PROGRAMMING TIP -- CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin: BITS SMB LD LD BITR LD LD EMB 15 EA,#10H PMG1,EA P2.0 A,#9H CLMOD,A ; P2.0 Output mode ; Clear P2.0 output latch
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S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
7
OVERVIEW
INTERRUPTS
The S3C72P9 interrupt control circuit has five functional components: -- Interrupt enable flags (IEx) -- Interrupt request flags (IRQx) -- Interrupt master enable register (IME) -- Interrupt priority register (IPR) -- Power-down release signal circuit Three kinds of interrupts are supported: -- Internal interrupts generated by on-chip processes -- External interrupts generated by external peripheral devices -- Quasi-interrupts used for edge detection and as clock sources
Table 7-1. Interrupt Types and Corresponding Port Pin (s) Interrupt Type External interrupts Internal interrupts Quasi-interrupts Interrupt Name INT0, INT1, INT4, INTK INTB, INTT0, INTT1, INTS INT2 INTW Corresponding Port Pins P1.0, P1.1, P1.3, K0-K7 Not applicable P1.2 Not applicable
7-1
INTERRUPTS
S3C72P9/P72P9 (Preliminary Spec)
Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. A vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (INTn) are set to logic one: -- Interrupt enable flag (IEx) -- Interrupt master enable flag (IME) -- Interrupt request flag (IRQx) -- Interrupt status flags (IS0, IS1) -- Interrupt priority register (IPR) If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction. The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the main routine, as well as during service routines. Any changes that are made to enable flag values during a service routine are not stored in the vector address. When an interrupt occurs, the EMB and the ERB flags before the interrupt is initiated are saved along with the program status word (PSW), and the EMB and the ERB flag for the interrupt is fetched from the respective vector address. Then, if necessary, you can modify the enable flags during the interrupt service routine. When the interrupt service routine is returned to the main routine by the IRET instruction, the original values saved in the stack are restored and the main program continues program execution with these values. Software-Generated Interrupts To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. Multiple Interrupts By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and thereby process multiple interrupts simultaneously. If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction. Power-Down Mode Release An interrupt can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. In such cases, the interrupt routine will not be executed since IME = "0".
7-2
S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
Interrupt is generated (INT xx)
Request flag (IRQx)
1
IEx = 1? Yes
No
Retain value until IEx = 1
Generate corresponding vector interrupt and release power-down mode
IME = 1? Yes Yes IS1, 0 = 0, 0? No IS1, 0 = 0, 1? Yes High-priority interrupt? Yes IS1, 0 = 0, 1 IS1, 0 = 1, 0
No
Retain value until IME= 1
Retain value until interrupt service routine is completed No
No
Store contents of PC and PSW in the stack area; set PC contents to corresponding vector address
Are both interrupt sources of shared vector address used? No
Yes
IRQx flag value remains 1
Reset corresponding IRQx flag
Jump to interrupt start address
Jump to interrupt start address
Verify interrupt source and clear IRQx with a BTSTZ instruction
Figure 7-1. Interrupt Execution Flowchart
7-3
INTERRUPTS
S3C72P9/P72P9 (Preliminary Spec)
IMOD1
IMOD0
IE2 IEW IETK IET1 IET0 IES IE1 IE0 IE4 IEB INTB IRQB IRQ4
INT4 INT0 INT1 @ INTS INTT0 INTT1 K0-K7 @ INTW IMODK INT2 @ @
IRQ0 IRQ1 IRQS IRQT0 IRQT1 IRQK IRQW IRQ2
IMOD2
Power-Down Mode Release Signal IME IPR Interrupt Control Unit IS1 IS0
@ = Edge Detection Circuit
Vector Interrupt Generator
Figure 7-2. Interrupt Control Circuit Diagram
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S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
Multiple Interrupts The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all interrupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. Two-Level Interrupt Handling Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see Figure 7-3). Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one and the values are stored in the stack along with the other PSW bits. After the interrupt routine has been serviced, the modified IS1 and IS0 values are automatically restored from the stack by an IRET instruction. IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable interrupt processing with a DI instruction. When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (IPR).
Normal Program Processing (Status 0) INT Disable Set IPR INT Enable Low or High Level Interrupt Generated
High or Low Level Interrupt Processing (Status 1) High Level Interrupt Processing (Status 2)
High Level Interrupt Generated
Figure 7-3. Two-Level Interrupt Handling
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INTERRUPTS
S3C72P9/P72P9 (Preliminary Spec)
Multi-Level Interrupt Handling With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1 (see Table 7-2). When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1" and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7-4). Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling Process Status 0 1 2 - Before INT IS1 0 0 1 1 IS0 0 1 0 1 All interrupt requests are serviced. Only high-priority interrupts as determined by the current settings in the IPR register are serviced. No additional interrupt requests will be serviced. Value undefined Effect of ISx Bit Setting After INT ACK IS1 0 1 - - IS0 1 0 - -
Normal Program Processing (Status 0) INT Disable Set IPR INT Enable Low or High Level Interrupt Generated
Single Interrupt 2-Level Interrupt
INT Disable Modify Status INT Enable Low or High Level Interrupt Generated
Status 1
3-Level Interrupt
Status 0 High Level Interrupt Generated Status 1 Status 2
Status 0
Figure 7-4. Multi-Level Interrupt Handling
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S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction. FB2H IME IPR.2 IPR.1 IPR.0
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. Table 7-3. Standard Interrupt Priorities Interrupt INTB, INT4 INT0 INT1 INTS INTT0 INTT1 INTK Default Priority 1 2 3 4 5 6 7
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the IME flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the current enable memory bank (EMB) value. Table 7-4. Interrupt Priority Register Settings IPR.2 0 0 0 0 1 1 1 1 IPR.1 0 0 1 1 0 0 1 1 IPR.0 0 1 0 1 0 1 0 1 Result of IPR Bit Setting Process all interrupt requests at low priority (note) Only INTB and INT4 interrupts are at high priority Only INT0 interrupts is at high priority Only INT1 interrupts is at high priority Only INTS interrupts is at high priority Only INTT0 interrupts is at high priority Only INTT1 interrupts is at high priority Only INTK interrupts is at high priority
NOTE: When all interrupts are low priority (the lower three bits of the IPR register are logic zero), the interrupt requested first will have high priority. Therefore, the first-request interrupt cannot be superceded by any other interrupt. If two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in Table 7-3 (the default priority assigned by hardware when the lower three IPR bits = "0"). In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the highpriority interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is started.
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INTERRUPTS
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Setting the INT Interrupt Priority
The following instruction sequence sets the INT1 interrupt to high priority: BITS SMB DI LD LD EI A,#3H IPR,A ; IPR.3 (IME) 1 EMB 15 ; IPR.3 (IME) 0
EXTERNAL INTERRUPT 0, 1 AND 2 MODE REGISTERS (IMOD0, IMOD1 AND IMOD2) The following components are used to process external interrupts at the INT0, INT1 and INT2 pins: -- Edge detection circuit -- Three mode registers, IMOD0, IMOD1 and IMOD2 The mode registers are used to control the triggering edge of the input signal. IMOD0, IMOD1 and IMOD2 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges. Since INT2 is a qusi-interrupt, the interrupt request flag (IRQ2) must be cleared by software. FB4H FB5H FDAH "0" "0" "0" "0" "0" "0" IMOD0.1 "0" "0" IMOD0.0 IMOD1.0 IMOD2.0
IMOD0, IMOD1 and IMOD2 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. Table 7-5. IMOD0, 1 and 2 Register Organization IMOD0 0 0 IMOD0.1 0 0 1 1 IMOD1 IMOD2 0 0 0 IMOD0.0 0 1 0 1 IMOD1.0 IMOD2.0 0 1 Effect of IMOD0 Settings Rising edge detection Falling edge detection Both rising and falling edge detection IRQ0 flag cannot be set to "1" Effect of IMOD1 and IMOD2 Settings Rising edge detection Falling edge detection
7-8
S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
EXTERNAL INTERRUPT 0, 1 and 2 MODE REGISTERS (Continued)
IMOD0 2 INT0 Edge Detection IRQ0
INT1
Edge Detection
IRQ1
INT2
Edge Detection
IRQ2
IMOD2 P1.2 P1.1 P1.0
IMOD1
Figure 7-5. Circuit Diagram for INT0, INT1 and INT2 Pins When modifying the IMOD registers, it is possible to accidentally set an interrupt request flag. To avoid unwanted interrupts, take these precautions when writing your programs: 1. Disable all interrupts with a DI instruction. 2. Modify the IMOD register. 3. Clear all relevant interrupt request flags. 4. Enable the interrupt by setting the appropriate IEx flag. 5. Enable all interrupts with an EI instructions.
7-9
INTERRUPTS
S3C72P9/P72P9 (Preliminary Spec)
EXTERNAL KEY INTERRUPT MODE REGISTER (IMODK) The mode register for external key interrupts at the K0-K7 pins, IMODK, is addressable only by 4-bit write instructions. RESET clears all IMODK bits to logic zero. FB6H "0" IMODK.2 IMODK.1 IMODK.0
Rising or falling edge can be detected by bit IMODK.2 settings. If a rising or falling edge is detected at any one of the selected K pin by the IMODK register, the IRQK flag is set to logic one and a release signal for power-down mode is generated. Table 7-6. IMODK Register Bit Settings IMODK 0 IMODK.2 0, 1 IMODK.1 0 0 1 1 IMODK.0 0 1 0 1 Effect of IMODK Settings Disable key interrupt Enable edge detection at the K0-K3 pins Enable edge detection at the K4-K7 pins Enable edge detection at the K0-K7 pins
IMODK.2
0 1
Falling edge detection Rising edge detection
NOTES: 1. To generate a key interrupt, the selected pins must be configured to input mode. If any one pin of the selected pins is configured to output mode, only falling edge can be detected. 2. To generate a key interrupt, all of the selected pins must be at input high state for falling edge detection, or all of the selected pins must be at input low state for rising edge detection. If any one of them or more is at input low state or input high state, the interrupt may be not occurred at falling edge or rising edge. 3. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select edge detection and pins by setting IMODK register.
7-10
S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
P6.3/K7
P6.2/K6 Enable/ Disable P6.1/K5 Rising/ Falling Edge Selector
P6.0/K4
IRQK
P0.3/K3
P0.2/K2 Enable/ Disable P0.1/K1
P0.0/K0
IMODK
Figure 7-6. Circuit Diagram for INTK
7-11
INTERRUPTS
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Using INTK as a Key Input Interrupt
When the key interrupt is used, the selected key interrupt source pin must be set to input: 1. When K0-K7 are selected (eight pins): BITS SMB LD LD LD LD LD LD LD EMB 15 A,#3H IMODK,A EA,#00H PMG1,EA PMG4,EA EA,#41H PUMOD1,EA ; Enable P0 and P6 pull-up resistors ; P0 input mode ; P6 input mode ; (IMODK) #3H, K0-K7 falling edge select
2. When K0-K3 are selected (four pins): BITS SMB LD LD LD LD LD LD EMB 15 A,#1H IMODK,A EA,#00H PMG1,EA EA,#1H PUMOD1,EA ; Enable P0 pull-up resistors ; P0 input mode ; (IMODK) #1H, K0-K3 falling edge select
7-12
S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
INTERRUPT FLAGS There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each interrupt, the interrupt master enable flag, which enables or disables all interrupt processing. Interrupt Master Enable Flag (IME) The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the IME flag is set to logic one. The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions, regardless of the current value of the enable memory bank flag (EMB). IME 0 1 Interrupt Enable Flags (IEx) IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled. Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag. Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses Address FB8H FBAH FBBH FBCH FBDH FBEH FBFH Bit 3 IE4 0 IEK 0 0 IE1 0 Bit 2 IRQ4 0 IRQK 0 0 IRQ1 0 Bit 1 IEB IEW IET1 IET0 IES IE0 IE2 Bit 0 IRQB IRQW IRQT1 IRQT0 IRQS IRQ0 IRQ2 IPR.2 IPR.1 IPR.0 Effect of Bit Settings Inhibit all interrupts Enable all interrupts
NOTES: 1. IEx refers to all interrupt enable flags. 2. IRQx refers to all interrupt request flags. 3. IEx = 0 is interrupt disable mode. 4. IEx = 1 is interrupt enable mode.
7-13
INTERRUPTS
S3C72P9/P72P9 (Preliminary Spec)
Interrupt Request Flags (IRQx) Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions.IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag. When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary, follow these guidelines for using IRQx flags: 1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of IRQW and IRQ2). 3. When IRQx is set to "1" by software, an interrupt is generated. When two interrupts share the same service routine start address, interrupt processing may occur in one of two ways: -- When only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been serviced. -- When two interrupts are enabled, the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared manually using a BTSTZ instruction.
Table 7-8. Interrupt Request Flag Conditions and Priorities Interrupt Source INTB INT4 INT0 INT1 INTS INTT0 INTT1 INTK INT2 INTW Internal / External I E E E I I I E E I Pre-condition for IRQx Flag Setting Reference time interval signal from basic timer Both rising and falling edges detected at INT4 Rising or falling edge detected at INT0 pin Rising or falling edge detected at INT1 pin Completion signal for serial transmit-and-receive or receive-only operation Signals for TCNT0 and TREF0 registers match Signals for TCNT1 and TREF1 registers match When a rising or falling edge detected at any one of the K0-K7 pins Rising or falling edge detected at INT2 Time interval of 0.5 secs or 3.19 msecs Interrupt Priority 1 1 2 3 4 5 6 7 - - IRQ Flag Name IRQB IRQ4 IRQ0 IRQ1 IRQS IRQT0 IRQT1 IRQK IRQ2 IRQW
7-14
S3C72P9/P72P9 (Preliminary Spec)
INTERRUPTS
+ PROGRAMMING TIP -- Enabling the INTB and INT4 Interrupts
To simultaneously enable INTB and INT4 interrupts: INTB DI BTSTZ JR * * * EI IRET ; INT4 BITR * * * EI IRET IRQ4 ; INT4 is processed IRQB INT4 ; IRQB = 1 ? ; If no, INT4 interrupt; if yes, INTB interrupt is processed
7-15
S3C72P9/P72P9 (Preliminary Spec)
POWER-DOWN
8
OVERVIEW
POWER-DOWN
The S3C72P9 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally. When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed, normal CPU operation resumes. In stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hardware components are powered-down. The effect of stop mode on specific peripheral hardware components -- CPU, basic timer, serial I/O, timer/ counters 0 and 1, watch timer, and LCD controller -- and on external interrupt requests, is detailed in Table 8-1. Idle or stop modes are terminated either by a RESET, or by an interrupt which is enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by RESET, a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. When an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (IME): -- If the IME flag = "0"; If the power down mode release signal is generated, after releasing the power-down mode, program execution starts immediately under the instruction to enter power down mode without execution of interrupt service routine. The interrupt request flag remains set to logic one. -- If the IME flag = "1"; If the power down mode release signal is generated, after releasing the power down mode, two instructions following the instruction to enter power down mode are executed first and the interrupt service routine is executed, finally program is resumed. However, when the release signal is caused by INT2 or INTW, the operation is identical to the IME = "0" condition because INT2 and INTW are a quasi-interrupt. NOTE Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage.
8-1
POWER-DOWN
S3C72P9/P72P9 (Preliminary Spec)
Table 8-1. Hardware Operation During Power-Down Modes Operation System clock status Stop Mode (STOP) STOP mode can be used only if the main system clock is selected as system clock (CPU clock) Main system clock oscillation stops Basic timer stops Operates only if external SCK input is selected as the serial I/O clock Operates only if TCL0 is selected as the counter clock Operates only if TCL1 is selected as the counter clock Operates only if subsystem clock (fxt) is selected as the counter clock Idle Mode (IDLE) Idle mode can be used if the main system clock or subsystem clock is selected as system clock (CPU clock) CPU clock oscillation stops (main and subsystem clock oscillation continues) Basic timer operates (with IRQB set at each reference interval) Operates if a clock other than the CPU clock is selected as the serial I/O clock Timer/counter 0 operates Timer/counter 1 operates Watch timer operates
Clock oscillator Basic timer Serial I/O interface Timer/counter 0 Timer/counter 1 Watch timer LCD controller External interrupts CPU Mode release signal
Operates only if a subsystem clock is se- LCD controller operates lected as LCDCK INTO, INT1, INT2, INT4, and INTK are acknowledged All CPU operations are disabled Interrupt request signals are enabled by an interrupt enable flag or by RESET input INT0, INT1, INT2, INT4 and INTK are acknowledged All CPU operations are disabled Interrupt request signals are enabled by an interrupt enable flag or by RESET input
8-2
S3C72P9/P72P9 (Preliminary Spec)
POWER-DOWN
Table 8-2. System Operating Mode Comparison Mode Main operating mode Condition Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. STOP/IDLE Mode Start Method - Current Consumption A
Main Idle mode
IDLE instruction
B
Main Stop mode Main oscillator runs. Sub oscillator runs. System clock is the main oscillation clock. Sub operating mode Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. Main oscillator runs. Sub oscillator is stopped by SCMOD.2. System clock is the main oscillation clock.
STOP instruction
D
-
C
Sub ldle Mode
IDLE instruction
D
Sub Stop mode
Setting SCMOD.2 to "1": This mode can be released only by an external RESET.
E
Main/Sub Stop mode
STOP instruction: This mode can be released by an interrupt and RESET.
E
NOTE: The current consumption is: A > B > C > D > E.
8-3
POWER-DOWN
S3C72P9/P72P9 (Preliminary Spec)
IDLE MODE TIMING DIAGRAMS
Idle Instruction RESET
Oscillator Stabilization Wait Time (31.3 ms/4.19 MHz)
Normal Mode
Idle Mode
Normal Mode
Clock Signal
Normal Oscillation
Figure 8-1. Timing When Idle Mode is Released by RESET
Idle Instruction Mode Release Signal Normal Mode Idle Mode Interrupt Acknowledge (IME = 1)
Normal Mode
Clock Signal
Normal Oscillation
Figure 8-2. Timing When Idle Mode is Released by an Interrupt
8-4
S3C72P9/P72P9 (Preliminary Spec)
POWER-DOWN
STOP MODE TIMING DIAGRAMS
Stop Instruction RESET
Oscillator Stabilization Wait Time (31.3 ms/4.19 MHz)
Normal Mode
Stop mode Oscillation Stops
Idle Mode
Normal Mode
Clock Signal
Oscillation Resumes
Figure 8-3. Timing When Stop Mode is Released by RESET
Stop Instruction Mode Release signal Normal Mode Stop mode Oscillation Stops
Oscillator Stabilization Wait Time (BMOD Setting) INT ACK (IME=1) Idle Mode Normal Mode
Clock Signal
Oscillation Resumes
Figure 8-4. Timing When Stop Mode is Released by an Interrupt
8-5
POWER-DOWN
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Reducing Power Consumption for Key Input Interrupt Processing
The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. In this example, the system clock source is switched from the main system clock to a subsystem clock and the LCD display is turned on: KEYCLK DI CALL SMB LD LD LD LD SMB BITR BITR BITS BITS CLKS1 CALL BTSTZ JR CALL subroutine EI RET CIDLE IDLE NOP NOP JPS CLKS1 ; Engage idle mode MA2SUB 15 EA,#00H P4,EA A,#3H IMODK,A 0 IRQW IRQK IEW IEK WATDIS IRQK CIDLE SUB2MA ; Subsystem clock main system clock switch ; Execute clock and display changing subroutine ; Select K0-K7 enable ; All key strobe outputs to low level ; Main system clock subsystem clock switch subroutine
8-6
S3C72P9/P72P9 (Preliminary Spec)
POWER-DOWN
RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 8-2. Table 8-3. Unused Pin Connections for Reducing Power Consumption Pin/Share Pin Names P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 P1.0/INT0-P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/LCDCK P2.2/LCDSY P3.0/TCLO0 P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 P4.0/COM8-P4.3/COM11 P5.0/COM12-P5.3/COM15 P6.0/SEG55/K4-P6.3/SEG52/K7 P7.0/SEG51-P7.3/SEG48 P8.0/SEG47-P8.3/SEG44 P9.0/SEG43-P9.3/SEG40 SEG0-SEG39 COM0-COM7 VLC1-VLC5 XTIN (note) XTOUT TEST Recommended Connection Input mode: Connect to VDD Output mode: No connection
Connect to VDD Connect to VDD Input mode: Connect to VDD Output mode: No connection
No connection No connection Stop sub-oscillator by setting the SCMOD.2 to logic "1" No connection Connect to VSS
NOTE: You can stop the sub-oscillator by setting the SCMOD.2 to one.
8-7
S3C72P9/P72P9 (Preliminary Spec)
RESET
9
OVERVIEW
-- Carry flag
RESET
When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has elapsed, normal system operation resumes. Regardless of when the RESET occurs -- during normal operating mode or during a power-down mode -- most hardware register values are set to the reset values described in Table 9-1. The current status of several register values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs during normal operating mode, their values are undefined. Current values that are retained in this case are as follows:
-- Data memory values -- General-purpose registers E, A, L, H, X, W, Z, and Y -- Serial I/O buffer register (SBUF)
RESET Input Normal Mode or Power-down Mode RESET Operation
Oscillator Stabilization Wait Time (31.3 ms/4.19 MHz)
Idle Mode
Operatng Mode
Figure 9-1. Timing for Oscillation Stabilization after RESET HARDWARE REGISTER VALUES AFTER RESET Table 9-1 gives you detailed information about hardware register values after a RESET occurs during powerdown mode or during normal operation.
9-1
RESET
S3C72P9/P72P9 (Preliminary Spec)
Table 9-1. Hardware Register Values After RESET Hardware Component or Subcomponent Program counter (PC) If RESET Occurs During Power-Down Mode Lower six bits of address 0000H are transferred to PC13-8, and the contents of 0001H to PC7-0. Retained 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Values retained Values retained (note) 0, 0 0 0 0 0 0 0 0 0 0 0 0 0 If RESET Occurs During Normal Operation Lower six bits of address 0000H are transferred to PC13-8, and the contents of 0001H to PC7-0. Undefined 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Undefined Undefined 0, 0 0 0 0 0 0 0 0 0 0 0 0 0
Program Status Word (PSW): Carry flag (C) Skip flag (SC0-SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB)
Stack pointer (SP) Data Memory (RAM): General registers E, A, L, H, X, W, Z, Y General-purpose registers Bank selection registers (SMB, SRB) BSC register (BSC0-BSC3) Clocks: Power control register (PCON) Clock output mode register (CLMOD) System clock mode register (SCMOD) Interrupts: Interrupt request flags (IRQx) Interrupt enable flags (IEx) Interrupt priority flag (IPR) Interrupt master enable flag (IME) INT0 mode register (IMOD0) INT1 mode register (IMOD1) INT2 mode register (IMOD2) INTK mode register (IMODK)
NOTE: The values of the 0F8H-0FDH are not retained when a RESET signal is input.
9-2
S3C72P9/P72P9 (Preliminary Spec)
RESET
Table 9-1. Hardware Register Values After RESET (Continued) Hardware Component or Subcomponent I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD1/2) Basic Timer: Count register (BCNT) Mode register (BMOD) Mode register (WDMOD) Counter clear flag (WDTCF) Timer/Counters 0 and 1: Count registers (TCNT0/1) Reference registers (TREF0/1) Mode registers (TMOD0/1) Output enable flags (TOE0/1) Watch Timer: Watch timer mode register (WMOD) LCD Driver/Controller: LCD contrast control register (LCNST) LCD mode register (LMOD) LCD control register (LCON) Display data memory Output buffers Serial I/O Interface: SIO mode register (SMOD) SIO interface buffer (SBUF) N-Channel Open-Drain Mode Register PNE0/3 0 0 0 Values retained 0 Undefined 0 0 0 Values retained Off 0 0 0 Undefined Off 0 0 0 FFH, FFFFH 0 0 0 FFH, FFFFH 0 0 Undefined 0 A5H 0 Undefined 0 A5H 0 Off 0 0 0 Off 0 0 0 If RESET Occurs During Power-Down Mode If RESET Occurs During Normal Operation
9-3
S3C72P9/P72P9 (Preliminary Spec)
I/O PORTS
10
OVERVIEW
Port Mode Flags
I/O PORTS
The S3C72P9 has 10 ports. There are total of 4 input pins and 35 configurable I/O pins, for a maximum number of 39 pins. Pin addresses for all ports are mapped to bank 15 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions.
Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. Pull-up Resistor Mode Register (PUMOD) The pull-up register mode registers (PUMOD1, 2) are used to assign internal pull-up resistors by software to specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.
10-1
I/O PORTS
S3C72P9/P72P9 (Preliminary Spec)
Table 10-1. I/O Port Overview Port 0 I/O I/O Pins 4 Pin Names P0.0-P0.3 Address FF0H Function Description 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. Individual pins are software configurable as open-drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test is possible. 4-bit pull-up resistors are assignable. Same as port 0 except that port 2 is 3-bit I/O port. Same as port 0. 4-bit I/O ports. 1-, 4-bit or 8-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as P4 and P5. Same as P4 and P5.
1
I
4
P1.0-P1.3
FF1H
2 3 4, 5
I/O I/O I/O
3 4 8
P2.0-P2.2 P3.0-P3.3 P4.0-P4.3 P5.0-P5.3
FF2H FF3H FF4H FF5H
6, 7 8, 9
I/O I/O
8 8
P6.0-P6.3 P7.0-P7.3 P8.0-P8.3 P9.0-P9.3
FF6H FF7H FF8H FF9H
Table 10-2. Port Pin Status During Instruction Execution Instruction Type 1-bit test 1-bit input 4-bit input 8-bit input 1-bit output 4-bit output 8-bit output Example BTST LDB LD LD BITR LD LD P0.1 C,P1.3 A,P7 EA,P4 P2.3 P2,A P6,EA Input Mode Status Input or test data at each pin Output Mode Status Input or test data at output latch
Output latch contents undefined Transfer accumulator data to the output latch
Output pin status is modified Transfer accumulator data to the output pin
10-2
S3C72P9/P72P9 (Preliminary Spec)
I/O PORTS
PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. For convenient program reference, PM flags are organized into five groups -- PMG1, PMG2, PMG3, PMG4 and PMG5 as shown in Table 10-3. They are addressable by 8-bit write instructions only. When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears all port mode flags to logical zero, automatically configuring the corresponding I/O ports to input mode. Table 10-3. Port Mode Group Flags PM Group ID PMG1 PMG2 PMG3 PMG4 PMG5 Address FE6H FE7H FE8H FE9H FEAH FEBH FECH FEDH FEEH FEFH Bit 3 PM0.3 "0" PM3.3 "0" PM4.3 PM5.3 PM6.3 PM7.3 PM8.3 PM9.3 Bit 2 PM0.2 PM2.2 PM3.2 "0" PM4.2 PM5.2 PM6.2 PM7.2 PM8.2 PM9.2 Bit 1 PM0.1 PM2.1 PM3.1 "0" PM4.1 PM5.1 PM6.1 PM7.1 PM8.1 PM9.1 Bit 0 PM0.0 PM2.0 PM3.0 "0" PM4.0 PM5.0 PM6.0 PM7.0 PM8.0 PM9.0
NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode: PM0.0 for P0.0, PM0.1 for P0.1, etc,. All flags are cleared to "0" following RESET.
+ PROGRAMMING TIP -- Configuring I/O Ports to Input or Output
Configure ports 0 and 2 as an output port: BITS SMB LD LD EMB 15 EA,#7FH PMG1,EA ; P0 and P2 Output
10-3
I/O PORTS
S3C72P9/P72P9 (Preliminary Spec)
PULL-UP RESISTOR MODE REGISTER (PUMOD) The pull-up resistor mode registers (PUMOD1 and PUMOD2) are used to assign internal pull-up resistors by software to specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting. PUMOD1 is addressable by 8-bit write instructions only, and PUMOD2 by 4-bit write instruction only. RESET clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up resistors. Table 10-4. Pull-Up Resistor Mode Register (PUMOD) Organization PUMOD ID PUMOD1 PUMOD2 Address FDCH FDDH FDEH Bit 3 PUR3 PUR7 "0" Bit 2 PUR2 PUR6 "0" Bit 1 PUR1 PUR5 PUR9 Bit 0 PUR0 PUR4 PUR8
NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2, and so on.
+ PROGRAMMING TIP -- Enabling and Disabling I/O Port Pull-Up Resistors
P6 and P7 enable pull-up resistors. BITS SMB LD LD EMB 15 EA,#0C0H PUMOD1,EA ; P6 and P7 enable
N-CHANNEL OPEN-DRAIN MODE REGISTER (PNE) The n-channel, open-drain mode register (PNE) is used to configure ports 0, 2 and 3 to n-channel, open-drain or as push-pull outputs. When a bit in the PNE register is set to "1", the corresponding output pin is configured to nchannel, open-drain; when set to "0", the output pin is configured to push-pull. The PNE register consists of an 8bit register and a 4-bit register; PNE0 can be addressed by 8-bit write instructions only and PNE3 by 4-bit write instructions only. FD6H FD7H FD8H PNE0.3 PNE2.3 PNE3.3 PNE0.2 PNE2.2 PNE3.2 PNE0.1 PNE2.1 PNE3.1 PNE0.0 PNE2.0 PNE3.0 PNE2 PNE1
10-4
S3C72P9/P72P9 (Preliminary Spec)
I/O PORTS
PORT 0 CIRCUIT DIAGRAM
VDD
PUR0 PM0.3 PUR0 PM0.2 PUR0 PM0.1 PUR0 PM0.0 SCK P0.0/SCK P0.1/SO P0.2/SI P0.3/BUZ Type B SO Type B Type B BUZ Type B Output Latch 1, 4
Type B PNE0.x VDD
CMOS Push-Pull, N-Channel Open-Drain
PM0.0 P-Ch Input Data PM0.x x=0-3 Output Data N-Ch PM0.2 SI SCK MUX 1, 4
NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (PUMOD).
Figure 10-1. Port 0 Circuit Diagram
10-5
I/O PORTS
S3C72P9/P72P9 (Preliminary Spec)
PORT 1 CIRCUIT DIAGRAM
VDD
INT0 INT1 INT2 INT4
PUMOD.1
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 N/R = Noise Reduction
Figure 10-2. Port 1 Circuit Diagram
10-6
S3C72P9/P72P9 (Preliminary Spec)
I/O PORTS
PORT 2 CIRCUIT DIAGRAM
VDD
PUR2 PM2.2 PUR2 PM2.1 PUR2 PM2.0 CLO P2.0/CLO P2.1/LCDCK P2.2/LCDSY Type B LCDCK Type B LCDSY Type B Output Latch 1, 4
Type B PNE2.x VDD
CMOS Push-Pull, N-Channel Open-Drain
P-Ch Input Data PM2.x x=0-2 Output Data N-Ch
PM2.0 MUX PM2.1 PM2.2 1, 4
NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (PUMOD).
Figure 10-3. Port 2 Circuit Diagram
10-7
I/O PORTS
S3C72P9/P72P9 (Preliminary Spec)
PORT 3 CIRCUIT DIAGRAM
VDD
PUR3 PM3.3 PUR3 PM3.2 PUR3 PM3.1 PUR3 PM3.0 TCLO0 P3.0/TCLO0 P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 Type B TCLO1 Type B Type B Type B Output Latch 1, 4
Type B PNE3.x VDD
CMOS Push-Pull, N-Channel Open-Drain
PM3.0 P-Ch Input Data PM3.x x=0-3 Output Data N-Ch TCL0 TCL1 NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (PUMOD). PM3.1 MUX 1, 4
Figure 10-4. Port 3 Circuit Diagram
10-8
S3C72P9/P72P9 (Preliminary Spec)
I/O PORTS
PORT 4, 5, 6, 7, 8, 9 CIRCUIT DIAGRAM
VDD
x = port number (4, 5, 6, 7, 8, 9) PURx PMx.3 PURx PMx.2 PURx PMx.1 PURx PMx.0
Px.0 Px.1 Px.2 Px.3
Output Latch
1, 4, 8
PMx.0 PMx.1 PMx.2 PMx.3 1, 4, 8
MUX
NOTE:
When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (PUMOD). Port 6 is a schmitt trigger input.
Figure 10-5. Ports 4, 5, 6, 7, 8, and 9 Circuit Diagram
10-9
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
11
OVERVIEW
-- Watch timer (WT)
TIMERS and TIMER/COUNTERS
The S3C72P9 microcontroller has four timer and timer/counter modules: -- 8-bit basic timer (BT) -- 8-bit timer/counter (TC0) -- 16-bit timer/counter (TC1)
The 8-bit basic timer (BT) is the microcontroller's main interval timer and watch-dog timer. It generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. The basic timer is also used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET. The 8-bit timer/counter (TC0) and the 16-bit timer/counter (TC1) are programmable timer/counters that are used primarily for event counting and for clock frequency modification and output. In addition, TC0 generates a clock signal that can be used by the serial I/O interface. The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. It also generates a clock signal for the LCD controller.
11-1
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
BASIC TIMER (BT)
OVERVIEW The 8-bit basic timer (BT) has six functional components: -- Clock selector logic -- 4-bit mode register (BMOD) -- 8-bit counter register (BCNT) -- 8-bit watchdog timer mode register (WDMOD) -- Watchdog timer counter clear flag (WDTCF) The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET. Bit settings in the basic timer mode register BMOD turns the BT module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. Interval Timer Function The basic timer's primary function is to measure elapsed time intervals. The standard time interval is equal to 256 basic timer clock pulses. To restart the basic timer, one bit setting is required: bit 3 of the mode register BMOD should be set to logic one. The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2-BMOD.0. The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs ( 255). An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time interval has elapsed. An interrupt request is than generated, BCNT is cleared to logic zero, and counting continues from 00H. Watchdog Timer Function The basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation error. For this purpose, instruction that clear the watchdog timer (BITS WDTCF) should be executed at proper points in a program within given period. If an instruction that clears the watchdog timer is not executed within the given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset status. An operation of watchdog timer is as follows: -- Write some values (except #5AH) to watchdog timer mode register, WDMOD. -- If WDCNT overflows, system reset is generated.
11-2
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
Oscillation Stabilization Interval Control Bits 2-0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also determines the time interval (also referred to as `wait time') required to stabilize clock signal oscillation when stop mode is released by an interrupt. When a RESET signal is inputted, the standard stabilization interval for system clock oscillation following the RESET is 31.3 ms at 4.19 MHz. Table 11-1. Basic Timer Register Overview Register Name BMOD Type Control Description Controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after stop mode release or RESET Counts clock pulses matching the BMOD frequency setting Controls watchdog timer operation. Clears the watchdog timer's counter. Size 4-bit RAM Address F85H Addressing Mode 4-bit write-only; BMOD.3: 1-bit writeable 8-bit read-only 8-bit write-only 1-, 4-bit write Reset Value "0"
BCNT WDMOD WDTCF
Counter Control Control
8-bit 8-bit 1-bit
F86H-F87H F98H-F99H F9AH.3
U(note) A5H "0"
NOTE: 'U' means the value is undetermined after a RESET.
11-3
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
"Clear" Signal Clear BCNT Clock Selector Overflow BCNT IRQB 1-Bit R/W 8 Clock Input 1 Pulse Period = BT Input Clock 28 (1/2 Duty) CPU Clock Start Signal (Power-Down Release) Clear IRQB Interrupt Request
BITS Instruction 4
BMOD.3 BMOD.2 BMOD.1 BMOD.0
3-Bit Counter WDCNT Clear WDMOD 8 WDTCF WAIT (note) RESET Stop Clear BITS Instruction DELAY Overflow Reset Signal Generation RESET
NOTES: 1. WAIT means stabilization time after RESET or stabilization time after STOP mode release. 2. The RESET signal can be generated if the WDMOD is toggled for 8 times where "toggle" means change from 5AH to other value and vice versa. 3. When the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to "0", the 3-bit counter of the watchdog timer (WDCNT) can be increased by 1. For example, when the BMOD value is x000B and the watchdog timer is enabled, the watchdog timer interval time is from 23 x 212 x 28/fxx to (23-1) x 212 x 28/fxx.
Figure 11-1. Basic Timer Circuit Diagram
11-4
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also 1-bit addressable. All BMOD values are set to logic zero following RESET and interrupt request signal generation is set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following effects: -- Restart the basic timer; -- Control the frequency of clock signal input to the basic timer; -- Determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency during program execution. Four BT frequencies, ranging from fxx/212 to fxx/25, are selectable. Since BMOD's reset value is logic zero, the default clock frequency setting is fxx/212. The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set to logic one by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt request flag (IRQB) are both cleared to logic zero, and timer operation restarts. The combination of bit settings in the remaining three registers -- BMOD.2, BMOD.1, and BMOD.0 -- determine the clock input frequency and oscillation stabilization interval. Table 11-2. Basic Timer Mode Register (BMOD) Organization BMOD.3 1 BMOD.2 0 0 1 1 BMOD.1 0 1 0 1 BMOD.0 0 1 1 1 Basic Timer Start Control Bit Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0" Basic Timer Input Clock fxx/212 (1.02 kHz) fxx/29 (8.18 kHz) fxx/27 (32.7 kHz) fxx/25 (131 kHz) Interrupt Interval Time (Wait Time) 220/fxx (250 ms) 217/fxx (31.3 ms) 215/fxx (7.82 ms) 213/fxx (1.95 ms)
NOTES 1. Clock frequencies and interrupt interval time assume a system oscillator clock frequency (fxx) of 4.19 MHz. 2. fxx = system clock frequency. 3. Wait time is the time required to stabilize clock signal oscillation after stop mode is released. The data in the table column "Interrupt Interval Time" can also be interpreted as "Oscillation Stabilization." 4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
11-5
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. RESET leaves the BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected. When BCNT has incrementing to hexadecimal `FFH' ( 255 clock pulses), it is cleared to `00H' and an overflow is generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals. NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the latter value as valid data. Until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met.
BASIC TIMER OPERATION SEQUENCE The basic timer's sequence of operations may be summarized as follows: 1. Set BMOD.3 to logic one to restart the basic timer. 2. BCNT is then incremented by one after each clock pulse corresponding to BMOD selection. 3. BCNT overflows if BCNT = 255 (BCNT = FFH). 4. When an overflow occurs, the IRQB flag is set by hardware to logic one. 5. The interrupt request is generated. 6. BCNT is then cleared by hardware to logic zero. 7. Basic timer resumes counting clock pulses.
11-6
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
+ PROGRAMMING TIP -- Using the Basic Timer
1. To read the basic timer count register (BCNT): BITS SMB LD LD LD CPSE JR EMB 15 EA,BCNT YZ,EA EA,BCNT EA,YZ BCNTR
BCNTR
2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: BITS SMB LD LD NOP STOP NOP NOP NOP EMB 15 A,#0BH BMOD,A
; Wait time is 31.3 ms ; Set stop power-down mode
CPU Operation
Normal Mode
Stop Mode
Idle Mode (31.3 ms)
Normal Mode
STOP Instruction
Stop Mode is Released by Interrupt
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz): BITS SMB LD LD EI BITS EMB 15 A,#0FH BMOD,A IEB ; Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer: BITS SMB BITS EMB 15 BMOD.3
11-7
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
WATCHDOG TIMER MODE REGISTER (WDMOD) The watchdog timer mode register, WDMOD, is a 8-bit write-only register. WDMOD register controls to enable or disable the watchdog function. WDMOD values are set to logic "A5H" following RESET and this value enables the watchdog timer. Watchdog timer is set to the longest interval because BT overflow signal is generated with the longest interval. WDMOD 5AH Any other value Watchdog Timer Enable/Disable Control Disable watchdog timer function Enable watchdog timer function
WATCHDOG TIMER COUNTER (WDCNT) The watchdog timer counter, WDCNT, is a 3-bit counter. WDCNT is automatically cleared to logic zero, and restarts whenever the WDTCF register control bit is set to "1". RESET, stop, and wait signal clears the WDCNT to logic zero also. WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is generated. When WDCNT has incremented to hexadecimal '07H', it is cleared to '00H' and an overflow is generated. The overflow causes the system RESET. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals. WATCHDOG TIMER COUNTER CLEAR FLAG (WDTCF) The watchdog timer counter clear flag, WDTCF, is a 1-bit write instruction. When WDTCF is set to one, it clears the WDCNT to zero and restarts the WDCNT. WDTCF register bits 2-0 are always logic zero. Table 11-3. Watchdog Timer Interval Time BMOD x000b x011b x101b x111b BT Input Clock fxx/212 fxx/29 fxx/27 fxx/25 WDT Interval Time (3) 23 x 212 x 28/fxx or (23-1) x 212 x 28/fxx 23 x 29 x 28/fxx or (23-1) x 29 x 28/fxx 23 x 27 x 28/fxx or (23-1) x 27 x 28/fxx 23 x 25 x 28/fxx or (23-1) x 25 x 28/fxx 1.75-2.0 sec 218.7-250 ms 54.6-62.5ms 13.6-15.6 ms
NOTES: 1. Clock frequencies assume a system oscillator clock frequency (fx) of 4.19 MHz 2. fxx = system clock frequency. 3. When the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to '0', the BCNT value is not cleared but increased continuously. As a result, the 3-bit counter of the watchdog timer (WDCNT) can be increased by 1. For example, when the BMOD value is x000b and the watchdog timer is enabled, the watchdog timer interval time is either 23 x 212 x 28/fxx or (23-1) x 212 x 28/fxx.
11-8
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
+ PROGRAMMING TIP -- Using the Watchdog Timer
RESET
MAIN
DI LD LD * * * LD LD * * * BITS * * * JP
EA,#00H SP,EA
A,#0DH BMOD,A
; WDCNT input clock is 7.82 ms
WDTCF
; Main routine operation period must be shorter than ; watchdog-timer's period
MAIN
11-9
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
8-BIT TIMER/COUNTER 0 (TC0)
OVERVIEW Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter value with the reference register value, TC0 can be used to measure specific time intervals. TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by counter logic. An 8-bit mode register, TMOD0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. To dynamically modify the basic frequency, new values can be loaded into the TMOD0 register during program execution.
TC0 FUNCTION SUMMARY 8-bit programmable timer External event counter Generates interrupts at specific time intervals based on the selected clock frequency. Counts various system "events" based on edge detection of external clock signals at the TC0 input pin, TCL0. To start the event counting operation, TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0". Outputs selectable clock frequencies to the TC0 output pin, TCLO0. Divides the frequency of an incoming external clock signal according to a modifiable reference value (TREF0), and outputs the modified frequency to the TCLO0 pin. Outputs a modifiable clock signal for use as the SCK clock source.
Arbitrary frequency output External signal divider
Serial I/O clock source
11-10
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC0 COMPONENT SUMMARY Mode register (TMOD0) Reference register (TREF0) Counter register (TCNT0) Clock selector circuit 8-bit comparator Activates the timer/counter and selects the internal clock frequency or the external clock source at the TCL0 pin. Stores the reference value for the desired number of clock pulses between interrupt requests. Counts internal or external clock pulses based on the bit settings in TMOD0 and TREF0. Together with the mode register (TMOD0), lets you select one of four internal clock frequencies or an external clock. Determines when to generate an interrupt by comparing the current value of the counter register (TCNT0) with the reference value previously programmed into the reference register (TREF0). Where a clock pulse is stored pending output to the serial I/O circuit or to the TC0 output pin, TCLO0. When the contents of the TCNT0 and TREF0 registers coincide, the timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is inverted, and an interrupt is generated. Output enable flag (TOE0) Interrupt request flag (IRQT0) Must be set to logic one before the contents of the TOL0 latch can be output to TCLO0. Cleared when TC0 operation starts and the TC0 interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide. Must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed. Table 11-4. TC0 Register Overview Register Name TMOD0 Type Control Description Controls TC0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6-4) Counts clock pulses matching the TMOD0 frequency setting Stores reference value for the timer/counter 0 interval setting Controls timer/counter 0 output to the TCLO0 pin Size 8-bit RAM Address F90H-F91H Addressing Mode 8-bit writeonly; (TMOD0.3 is also 1-bit writeable) 8-bit read-only 8-bit write-only 1/4-bit read/write Reset Value "0"
Output latch (TOL0)
Interrupt enable flag (IET0)
TCNT0 TREF0 TOE0
Counter Reference Flag
8-bit 8-bit 1-bit
F94H-F95H F96H-F97H F92H.2
"0" FFH "0"
11-11
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
Clocks (fxx/210, fxx/26, fxx/24, fxx) TCL0 TMOD0.7 TMOD0.6 TMOD0.5 8 TMOD0.4 Clear TMOD0.3 TMOD0.2 TMOD0.1 TMOD0.0 Clear Set Clear Inverted TOL0 Serial I/O TCLO0 Clock Selector 8 TCNT0 8-Bit Comparator 8 TREF0
IRQT0
PM3.0
P3.0 Latch
TOE0
Figure 11-2. TC0 Circuit Diagram TC0 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 0 -- Set TMOD0.2 to logic one. -- Set the TC0 interrupt enable flag IET0 to logic one. -- Set TMOD0.3 to logic one. TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts. Disable Timer/Counter 0 -- Set TMOD0.2 to logic zero. Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read if necessary.
11-12
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select the clock frequency. The reference register TREF0 stores the value for the number of clock pulses to be generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated. To program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF0 register. TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMOD0.4-TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag (IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0 is then cleared to 00H and TC0 continues counting. The interrupt request mechanism for TC0 includes an interrupt enable flag (IET0) and an interrupt request flag (IRQT0). TC0 OPERATION SEQUENCE The general sequence of operations for using TC0 can be summarized as follows: 1. Set TMOD0.2 to "1" to enable TC0. 2. Set TMOD0.6 to "1" to enable the system clock (fxx) input. 3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fxx/2n). 4. Load a value to TREF0 to specify the interval between interrupt requests. 5. Set the TC0 interrupt enable flag (IET0) to "1". 6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting. 7. TCNT0 increments with each internal clock pulse. 8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1" and an interrupt request is generated. 9. Output latch (TOL0) logic toggles high or low. 10. TCNT0 is cleared to 00H and counting resumes. 11. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".
11-13
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
TC0 EVENT COUNTER FUNCTION Timer/counter 0 can monitor or detect system 'events' by using the external clock input at the TCL0 pin as the counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals. The counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs. With the exception of the different TMOD0.4-TMOD0.6 settings, the operation sequence for TC0's event counter function is identical to its programmable timer/counter function. To activate the TC0 event counter function, -- Set TMOD0.2 to "1" to enable TC0. -- Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin. -- Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5 and TMOD0.4. -- P3.2 must be set to input mode.
Table 11-5. TMOD0 Settings for TCL0 Edge Detection TMOD0.5 0 0 TMOD0.4 0 1 TCL0 Edge Detection Rising edges Falling edges
11-14
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC0 CLOCK FREQUENCY OUTPUT Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is selected by loading the desired reference value into the reference register TREF0. To enable the output to the TCLO0 pin, the following conditions must be met: -- TC0 output enable flag TOE0 must be set to "1". -- I/O mode flag for P3.0 (PM3.0) must be set to output mode ("1"). -- Output latch value for P3.0 must be set to "0". In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as follows: 1. Load a reference value to TREF0. 2. Set the internal clock frequency in TMOD0. 3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1"). 4. Set P3.0 mode flag (PM3.0) to "1". 5. Set P3.0 output latch to "0". 6. Set TOE0 flag to "1". Each time TCNT0 overflows and an interrupt request is generated, the state of the output latch TOL0 is inverted and the TC0-generated clock signal is output to the TCLO0 pin.
+ PROGRAMMING TIP -- TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin: BITS SMB LD LD LD LD LD LD BITR BITS EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA EA,#01H PMG2,EA P3.0 TOE0 ; P3.0 output mode ; P3.0 clear
11-15
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
TC0 SERIAL I/O CLOCK GENERATION Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register, SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface. Use TMOD0 and TREF0 register settings to select the frequency and interval of the TC0 clock signals to be used as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock selector circuit (the TOE0 flag may be disabled). TC0 EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the TCLO0 pin. The sequence of operations used to divide external clock input can be summarized as follows: 1. Load a signal divider value to the TREF0 register. 2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin. 3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection. 4. Set port 3.0 mode flag (PM3.0) to output ("1"). 5. Set P3.0 output latch to "0". 6. Set TOE0 flag to "1" to enable output of the divided frequency to the TCLO0 pin.
+ PROGRAMMING TIP -- External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divided by four):
External (TCL0) Clock Pulse
TCLO0 Output Pulse
BITS SMB LD LD LD LD LD LD BITR BITS
EMB 15 EA,#01H TREF0,EA EA,#0CH TMOD0,EA EA,#01H PMG2,EA P3.0 TOE0
; P3.0 output mode ; P3.0 clear
11-16
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations. F90H F91H TMOD0.3 "0" TMOD0.2 TMOD0.6 "0" TMOD0.5 "0" TMOD0.4
TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are retained until TC0 is re-enabled. The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This selection involves two variables: -- Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal input at the TCL0 pin, and -- Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal TC0 operation. Table 11-6. TC0 Mode Register (TMOD0) Organization Bit Name TMOD0.7 TMOD0.6 TMOD0.5 TMOD0.4 TMOD0.3 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is automatically cleared to logic zero immediately after counting resumes.) Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0 Always logic zero Always logic zero F90H Setting 0 0,1 Always logic zero Specify input clock edge and internal frequency Resulting TC0 Function Address F91H
TMOD0.2 TMOD0.1 TMOD0.0
0 1 0 0
11-17
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
Table 11-7. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings TMOD0.6 0 0 1 1 1 1 TMOD0.5 0 0 0 0 1 1 TMOD0.4 0 1 0 1 0 1 Resulting Counter Source and Clock Frequency External clock input (TCL0) on rising edges External clock input (TCL0) on falling edges fxx/210 (4.09 kHz) fxx /26 (65.5 kHz) fxx/24 (262 kHz) fxx (4.19 MHz)
NOTE: 'fxx' = selected system clock of 4.19 MHz.
+ PROGRAMMING TIP -- Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS IET0 EMB 15 EA,#4CH TMOD0,EA
2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation: BITS SMB BITS EMB 15 TMOD0.3
11-18
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC0 COUNTER REGISTER (TCNT0) The 8-bit counter register for timer/counter 0, TCNT0, is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero (00H). Whenever TMOD0.3 is enabled, TCNT0 is cleared to logic zero and counting resumes. The TCNT0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4). Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 refer-ence buffer, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag, IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed.
~ ~
TREF0
Reference Value = n
~~ ~~
TCNT0
0
1
2
n-1
n
~~ ~~
~ ~
0 Match 1 2 n-1 n
Count Clock
0 Match
1
2
3
~ ~
TOL0
Interval Time
Timer Start Instruction (TMOD0.3 is set)
IRQT0 Set
~ ~
IRQT0 Set
Figure 11-3. TC0 Timing Diagram
11-19
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
TC0 REFERENCE REGISTER (TREF0) The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control instructions. RESET initializes the TREF0 value to 'FFH'. TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used to perform -- as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. During timer/counter operation, the value loaded into the reference register is compared to the TCNT0 value. When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal the interval or event. The TREF0 value, together with the TMOD0 clock frequency selection, determines the specific TC0 timer interval. Use the following formula to calculate the correct value to load to the TREF0 reference register: 1 TC0 timer interval = (TREF0 value + 1) x TMOD0 frequency setting (TREF0 value 0) TC0 OUTPUT ENABLE FLAG (TOE0) The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0 is addressable by 1-bit read and write instructions. (MSB) F92H TOE1
NOTE:
(LSB) TOE0 "U" "0"
The "U" means that the bit is undefined.
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled, timer/counter 0 can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock selector circuit. TC0 OUTPUT LATCH (TOL0) TOL0 is the output latch for timer/counter 0. When the 8-bit comparator detects a correspondence between the value of the counter register TCNT0 and the reference value stored in the TREF0 register, the TOL0 value is inverted -- the latch toggles high-to-low or low-to-high. Whenever the state of TOL0 is switched, the TC0 signal is output. TC0 output may be directed to the TCLO0 pin, or it can be output directly to the serial I/O clock selector circuit as the SCK signal. Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero, along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately. When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if necessary.
11-20
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
+ PROGRAMMING TIP -- Setting a TC0 Timer Interval
To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps. 1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter clock = fxx/210, and TREF0 is set to FFH): 2. Calculate the TREF0 value: 30 ms = TREF0 value + 1 4.09 kHz 30 ms 244 s = 122.9 = 7AH
TREF0 + 1 =
TREF0 value = 7AH - 1 = 79H 3. Load the value 79H to the TREF0 register: BITS SMB LD LD LD LD EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA
11-21
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
16-BIT TIMER/COUNTER
OVERVIEW Timer/counter 1 (TC1) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC1 generates an interrupt request. By counting signal transitions, it can be used to measure time intervals. The TC1 circuit also has 16-bit comparator logic. TC1 has a reloadable counter that consists of two parts: a 16-bit reference register (TREF1) into which you can write data for use as a reference value, and a 16-bit counter register (TCNT1) whose contents are automatically incremented by counter logic. The 8-bit mode register, TMOD1, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. You can modify the basic frequency dynamically by loading new values into TMOD1 during program execution. The only functional differences between TC0 and TC1 are the size of the counter and reference value registers (8-bit versus 16-bit), and the fact that only TC0 can generate a clock signal for the serial I/O interface. TIMER/COUNTER 1 FUNCTION SUMMARY 16-bit programmable timer External event counter Arbitrary frequency output External signal divider Generates interrupts at specific time intervals based on the selected clock frequency. Counts various system "events" based on edge detection of external clock signals at the TC1 input pin, TCL1. Outputs selectable clock frequencies to the TC1 output pin, TCLO1. Divides the frequency of an incoming external clock signal according to the modifiable reference value (TREF1), and outputs the modified frequency to the TCLO1 pin.
11-22
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TIMER/COUNTER 1 COMPONENT SUMMARY Mode register (TMOD1) Reference register (TREF1) Counter register (TCNT1) Clock selector circuit 16-bit comparator Activates the timer/counter and selects the internal clock frequency or the external clock source at the TCL1 pin. Stores the reference value for the desired number of clock pulses between interrupt requests. Counts internal clock pulses that are generated based on bit settings in the mode register and reference register. Together with the mode register (TMOD1), lets you select one of four internal clock frequencies, or the external system clock source. Determines when to generate an interrupt by comparing the current value of the counter (TCNT1) with the reference value previously programmed into the reference register (TREF1). Where a TC1 clock pulse is stored pending output to the TC1 output pin, TCLO1. When the contents of the TCNT1 and TREF1 registers coincide, the timer/counter interrupt request flag (IRQT1) is set to "1", the status of TOL1 is inverted, and an interrupt is generated. Must be set to logic one before the contents of the TOL1 latch can be output to TCLO1. Cleared when TC1 operation starts and set to logic one whenever the counter value and reference value match. Must be set to logic one before the interrupt requests generated by timer/counter 1 can be processed. Table 11-8. TC1 Register Overview Register Name TMOD1 Type Control Description Controls TC1 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and the clock frequency (bits 6-4) Counts clock pulses matching the TMOD1 frequency setting Stores reference value for TC1 interval setting Controls TC1 output to the TCLO1 pin Size 8-bit RAM Address FA0H-FA1H Addressing Mode 8-bit writeonly; (TMOD1.3 is also 1-bit writeable) 8-bit read-only 8-bit write-only 1/4-bit read/write Reset Value "0"
Output latch (TOL1)
Output enable flag (TOE1) Interrupt request flag (IRQT1) Interrupt enable flag (IET1)
TCNT1 TREF1 TOE1
Counter Reference Flag
16-bit 16-bit 1-bit
FA4H-FA5H, FA6H-FA7H FA8H-FA9H, FAAH-FABH F92H.3
"0" FFFFH "0"
11-23
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
Clocks (fxx/210, fxx/28, fxx/26, fxx/24) TCL1 TMOD1.7 TMOD1.6 TMOD1.5 8 TMOD1.4 Clear TMOD1.3 TMOD1.2 TMOD1.1 TMOD1.0 Clear Set Clear Inverted TOL1 Clock Selector 16 TCNT1 16-Bit Comparator 16 TREF1
IRQT1
TCLO1
PM3.1
P3.1 Latch
TOE1
Figure 11-4. TC1 Circuit Diagram TC1 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 1 -- Set the TC1 interrupt enable flag IET1 to logic one. -- Set TMOD1.3 to logic one. TCNT1, IRQT1, and TOL1 are cleared to logic zero, and timer/counter operation starts. Disable Timer/Counter 1 -- Set TMOD1.2 to logic zero. Clock signal input to the counter register TCNT1 is halted. The current TCNT1 value is retained and can be read if necessary.
11-24
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC1 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 1 can be programmed to generate interrupt requests at variable intervals, based on the system clock frequency you select. The 8-bit TC1 mode register, TMOD1, is used to activate the timer/counter and to select the clock frequency; the 16-bit reference register, TREF1, is used to store the value for the desired number of clock pulses between interrupt requests. The 16-bit counter register, TCNT1, counts the incoming clock pulses, which are compared to the TREF1 value. When there is a match, an interrupt request is generated. To program timer/counter 1 to generate interrupt requests at specific intervals, select one of the four internal clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF1 register. TCNT1 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMOD1.4-TMOD1.6 settings. To generate an interrupt request, the TC1 interrupt request flag (IRQT1) is set to logic one, the status of TOL1 is inverted, and the interrupt is output. The content of TCNT1 is then cleared to 0000H, and TC1 continues counting. The interrupt request mechanism for TC1 includes an interrupt enable flag (IET1) and an interrupt request flag (IRQT1). TC1 TIMER/COUNTER OPERATION SEQUENCE The general sequence of operations for using TC1 can be summarized as follows: 1. Set TMOD1.2 to "1" to enable TC1. 2. Set TMOD1.6 to "1" to enable the system clock (fxx) input. 3. Set TMOD1.5 and TMOD1.4 bits to desired internal frequency (fxx/2n). 4. Load a value to TREF1 to specify the interval between interrupt requests. 5. Set the TC1 interrupt enable flag (IET1) to "1". 6. Set TMOD1.3 bit to "1" to clear TCNT1, IRQT1, and TOL1, and start counting. 7. TCNT1 increments with each internal clock pulse. 8. When the comparator shows TCNT1 = TREF1, the IRQT1 flag is set to "1" and an interrupt request is generated. 9. Output latch (TOL1) logic toggles high or low. 10. TCNT1 is cleared to 0000H and counting resumes. 11. Programmable timer/counter operation continues until TMOD1.2 is cleared to "0".
11-25
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
TC1 EVENT COUNTER FUNCTION Timer/counter 1 can monitor system 'events' by using the external clock input at the TCL1 pin as the counter source. The TC1 mode register selects rising or falling edge detection for incoming clock signals. The counter register TCNT1 is incremented each time the selected state transition of the external clock signal occurs. With the exception of the different TMOD1.4-TMOD1.6 settings, the operation sequence for TC1's event counter function is identical to its programmable timer/counter function. To activate the TC1 event counter function, -- Set TMOD1.2 to "1" to enable TC1. -- Clear TMOD1.6 to "0" to select the external clock source at the TCL1 pin. -- Select TCL1 edge detection for rising or falling signal edges by loading the appropriate values to TMOD1.5 and TMOD1.4. -- Pin P3.3 must be set to input mode.
Table 11-9. TMOD1 Settings for TCL1 Edge Detection TMOD1.5 0 0 TMOD1.4 0 1 TCL1 Edge Detection Rising edges Falling edges
11-26
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC1 CLOCK FREQUENCY OUTPUT Using timer/counter 1, a modifiable clock frequency can be output to the TC1 clock output pin, TCLO1. To select the clock frequency, load the appropriate values to the TC1 mode register, TMOD1. The clock interval is selected by loading the desired reference value into the 16-bit reference register TREF1. To enable the output to the TCLO1 pin at I/O port 3.1, the following conditions must be met: -- TC1 output enable flag TOE1 must be set to "1". -- I/O mode flag for P3.1 (PM3.1) must be set to output mode ("1"). -- P3.1 output latch must be cleared to "0". In summary, the operational sequence required to output a TC1-generated clock signal to the TCLO1 pin is as follows: 1. Load your reference value to TREF1. 2. Set the internal clock frequency in TMOD1. 3. Initiate TC1 clock output to TCLO1 (TMOD1.2 = "1"). 4. Set port 3.1 mode flag (PM3.1) to "1". 5. Clear the P3.1 output latch. 6. Set TOE1 flag to "1". Each time TCNT1 overflows and an interrupt request is generated, the state of the output latch TOL1 is inverted and the TC1-generated clock signal is output to the TCLO1 pin.
+ PROGRAMMING TIP -- TC1 Signal Output to the TCLO1 Pin
Output a 30 ms pulse width signal to the TCLO1 pin: BITS SMB LD LD LD LD LD LD LD LD BITR BITS EMB 15 EA,#79H TREF1A,EA EA,#00H TREF1B,EA EA,#4CH TMOD1,EA EA,#02H PMG2,EA P3.1 TOE1 ; P3.1 output mode ; P3.1 clear
11-27
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
TC1 EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TC1 reference register, TREF1, you can divide the incoming clock signal by the TREF1 value and then output this modified clock frequency to the TCLO1 pin. The sequence of operations used to divide external clock input and output the signals to the TCLO1 pin can be summarized as follows: 1. Load a signal divider value to the TREF1 register. 2. Clear TMOD1.6 to "0" to enable external clock input at the TCLO1 pin. 3. Set TMOD1.5 and TMOD1.4 to desired TCL signal edge detection. 4. Set P3.1 mode flag (PM3.1) to output ("1"). 5. Clear the P3.1 output latch. 6. Set TOE1 flag to "1" to enable output of the divided frequency.
+ PROGRAMMING TIP -- External TCL1 Clock Output to the TCLO1 Pin
Output the external TCL1 clock source to the TCLO1 pin (divide by four):
External (TCL1) Clock Pulse
TCLO1 Output Pulse
BITS SMB LD LD LD LD LD LD LD LD BITR BITS
EMB 15 EA,#01H TREF1A,EA EA,#00H TREF1B,EA EA,#0CH TMOD1,EA EA,#02H PMG2,EA P3.1 TOE1 ; P3.1 output mode ; P3.1 clear
11-28
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC1 MODE REGISTER (TMOD1) TMOD1 is the 8-bit mode register for timer/counter 1. It is addressable by 8-bit write instructions. The TMOD1.3 bit is also 1-bit write addressable. RESET clears all TMOD1 bits to logic zero. Following a RESET, timer/counter 1 is disabled. FA0H FA1H TMOD1.3 "0" TMOD1.2 TMOD1.6 "0" TMOD1.5 "0" TMOD1.4
TMOD1.2 is the enable/disable bit for timer/counter 1. When TMOD1.3 is set to "1", the contents of TCNT1, IRQT1, and TOL1 are cleared, counting starts from 0000H, and TMOD1.3 is automatically reset to "0" for normal TC1 operation. When TC1 operation stops (TMOD1.2 = "0"), the contents of the TC1 counter register, TCNT1, are retained until TC1 is re-enabled. The TMOD1.6, TMOD1.5, and TMOD1.4 bit settings are used together to select the TC1 clock source. This selection involves two variables: -- Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal input at the TCL1 pin, and -- Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal TC1 operations.
Table 11-10. TC1 Mode Register (TMOD1) Organization Bit Name TMOD1.7 TMOD1.6 TMOD1.5 TMOD1.4 TMOD1.3 1 Clear TCNT1, IRQT1, and TOL1 and resume counting immediately (This bit is automatically cleared to logic zero immediately after counting resumes). Disable timer/counter 1; retain TCNT1 contents Enable timer/counter 1 Always logic zero Always logic zero FA0H Setting 0 0,1 Always logic zero Specify input clock edge and internal frequency FA1H Resulting TC1 Function Address
TMOD1.2 TMOD1.1 TMOD1.0
0 1 0 0
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TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
Table 11-11. TMOD1.6, TMOD1.5, and TMOD1.4 Bit Settings TMOD1.6 0 0 1 1 1 1 TMOD1.5 0 0 0 0 1 1 TMOD1.4 0 1 0 1 0 1 Resulting Counter Source and Clock Frequency External clock input (TCL1) on rising edges External clock input (TCL1) on falling edges fxx/210 (4.09 kHz) fxx/28 (16.4 kHz) fxx/26 (65.5 kHz) fxx/24 (262 kHz)
NOTE: 'fxx' = selected system clock of 4.19 MHz.
+ PROGRAMMING TIP -- Restarting TC1 Counting Operation
1. Set TC1 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS IET1 EMB 15 EA,#4CH TMOD1,EA
2. Clear TCNT1, IRQT1, and TOL1 and restart TC1 counting operation: SBITS SMB BITS EMB 15 TMOD1.3
11-30
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC1 COUNTER REGISTER (TCNT1) The 16-bit counter register for timer/counter 1, TCNT1, is mapped to RAM addresses FA5H-FA4H (TCNT1A) and FA7H-FA6H (TCNT1B). The two 8-bit registers are read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT1 register values to logic zero (00H). Whenever TMOD1.2 and TMOD1.3 are enabled, TCNT1 is cleared to logic zero and counting begins. The TCNT1 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMOD1 register (specifically, TMOD1.6, TMOD1.5, and TMOD1.4). Each time TCNT1 is incremented, the new value is compared to the reference value stored in the TC1 reference register, TREF1. When TCNT1 = TREF1, an overflow occurs in the TCNT1 register, the interrupt request flag, IRQT1, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed.
~ ~
TREF1
Reference Value = n
~~ ~~
TCNT1
0
1
2
n-1
n
~~ ~~
~ ~
0 Match 1 2 n-1 n
Count Clock
0 Match
1
2
3
TOL1 Interval Time
Timer Start Instruction (TMOD1.3 is set)
IRQT1 Set
~ ~
IRQT1 Set
Figure 11-5. TC1 Timing Diagram
11-31
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
TC1 REFERENCE REGISTER (TREF1) The TC1 reference register TREF1 is a 16-bit write-only register that is mapped to RAM locations FA9H-FA8H (TREF1A) and FABH-FAAH (TREF1B). It is addressable by 8-bit RAM control instructions. RESET clears the TREF1 value to 'FFFFH'. TREF1 is used to store a reference value to be compared to the incrementing TCNT1 register in order to identify an elapsed time interval. Reference values will differ depending upon the specific function that TC1 is being used to perform -- as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. During timer/counter operation, the value loaded into the reference register compared to the TCNT1 value. When TCNT1 = TREF1, the TC1 output latch (TOL1) is inverted and an interrupt request is generated to signal the interval or event. The TREF1 value, together with the TMOD1 clock frequency selection, determines the specific TC1 timer interval. Use the following formula to calculate the correct value to load to the TREF1 reference register: 1 TC1 timer interval = (TREF1 value + 1) x TMOD1 frequency setting (TREF1 value 0) TC1 OUTPUT ENABLE FLAG (TOE1) The 1-bit timer/counter 1 output enable flag TOE1 flag controls output from timer/counter 1 to the TCLO1 pin. TOE1 is addressable by 1-bit read and write instructions. Bit 3 F92H TOE1
NOTE:
Bit 2 TOE0
Bit 1 "U"
Bit 0 "0"
The "U" means that the bit is undefined.
When you set the TOE1 flag to "1", the contents of TOL1 can be output to the TCLO1 pin. Whenever a RESET occurs, TOE1 is automatically set to logic zero, disabling all TC1 output. TC1 OUTPUT LATCH (TOL1) TOL1 is the output latch for timer/counter 1. When the 16-bit comparator detects a correspondence between the value of the counter register TCNT1 and the reference value stored in the TREF1 register, the TOL1 logic toggles high-to-low or low-to-high. Whenever the state of TOL1 is switched, the TC1 signal exits the latch for output. TC1 output is directed (if TOE1 = "1") to the TCLO1 pin at I/O port 3.1. When timer/counter 1 is started, (TMOD1.3 = "0"), the contents of the output latch are cleared automatically. However, when TC1 is disabled (TMOD1.2 = "0"), the contents of the TOL1 latch are retained and can be read, if necessary.
11-32
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
+ PROGRAMMING TIP -- Setting a TC1 Timer Interval
To set a 30 ms timer interval for TC1, given fxx = 4.19 MHz, follow these steps: 1. Select the timer/counter 1 mode register with a maximum setup time of 16 seconds; assume the TC1 counter clock = fxx/210 and TREF1 is set to FFFFH. 2. Calculate the TREF1 value: 30 ms = TREF1 value + 1 4.09 kHz 30 ms 244 s = 122.9 = 7AH
TREF1 + 1 =
TREF1 value = 7AH - 1 = 79H 3. Load the value 79H to the TREF1 register: BITS SMB LD LD LD LD LD LD EMB 15 EA,#79H TREF1A,EA EA,#00H TREF1B,EA EA,#4CH TMOD1,EA
11-33
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
WATCH TIMER
OVERVIEW The watch timer is a multi-purpose timer which consists of three basic components: -- 8-bit watch timer mode register (WMOD) -- Clock selector -- Frequency divider circuit Watch timer functions include real-time and watch-time measurement and interval timing for the main and subsystem clock. It is also used as a clock source for the LCD controller and for generating buzzer (BUZ) output. Real-Time and Watch-Time Measurement To start watch timer operation, set bit 2 of the watch timer mode register (WMOD.2) to logic one. The watch timer starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. Using a Main System or Subsystem Clock Source The watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. When the zero bit of the WMOD register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if WMOD.0 = "0", the main system clock (fx) is used as the signal source, according to the following formula: Main system clock (fx) 128
Watch timer clock (fw) =
= 32.768 kHz (fx = 4.19 MHz)
This feature is useful for controlling timer-related operations during stop mode. When stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. By using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag IRQW to "1", thereby releasing stop mode. Clock Source Generation for LCD Controller The watch timer supplies the clock frequency for the LCD controller (fLCD). Therefore, if the watch timer is disabled, the LCD controller does not operate.
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S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the desired BUZ frequency , load the appropriate value to the WMOD register. This output can then be used to actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met: -- The WMOD.7 register bit is set to "1" -- The output latch for I/O port 0.3 is cleared to "0" -- The port 0.3 output mode flag (PM0.3) set to 'output' mode Timing Tests in High-Speed Mode By setting WMOD.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. Highspeed mode is useful for timing events for program debugging sequences. Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the input level at the XTin pin is high; if WMOD.3 is "0", the input level at the XTin pin is low.
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TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
WMOD.7
P0.3 Latch
PM0.3
WMOD.6
BUZ
WMOD.5 MUX
WMOD.4 8 WMOD.3 ENABLE/DISABLE WMOD.2
fw/2 (16 kHz) fw/4 (8 kHz) fw/8 (4 kHz) fw/16 (2 kHz) Selector Circuit
WMOD.1
IRQW
WMOD.0 fw/27 Clock Selector fw (32.768 kHz) Frequency Dividing Circuit fw/23 (4096Hz) fx = Main-system Clock fxt = Sub-system Clock fw = Watch Timer Frequency fLCD fw/214 (2 Hz)
fxt
fx/128
Figure 11-6. Watch Timer Circuit Diagram
11-36
S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only addressable. An exception is WMOD bit 3 (the XTIN input level control bit) which is 1-bit read-only addressable.
A RESET automatically sets WMOD.3 to the current input level of the subsystem clock, XTIN (high, if logic one; low, if logic zero), and all other WMOD bits to logic zero. F88H F89H WMOD.3 WMOD.7 WMOD.2 "0" WMOD.1 WMOD.5 WMOD.0 WMOD.4
In summary, WMOD settings control the following watch timer functions: -- Watch timer clock selection -- Watch timer speed control -- Enable/disable watch timer -- XTIN input level control -- Buzzer frequency selection -- Enable/disable buzzer output (WMOD.0) (WMOD.1) (WMOD.2) (WMOD.3) (WMOD.4 and WMOD.5) (WMOD.7)
Table 11-12. Watch Timer Mode Register (WMOD) Organization Bit Name WMOD.7 Values 0 1 WMOD.6 WMOD.5 - .4 0 0 1 1 WMOD.3 0 1 WMOD.2 WMOD.1 WMOD.0 0 1 0 1 0 1 0 0 1 0 1 Function Disable buzzer (BUZ) signal output at the BUZ pin Enable buzzer (BUZ) signal output at the BUZ pin Always logic zero 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output Input level to XTIN pin is low Input level to XTIN pin is high Disable watch timer; clear frequency dividing circuits Enable watch timer Normal mode; sets IRQW to 0.5 seconds High-speed mode; sets IRQW to 3.91 ms Select (fx/128 ) as the watch timer clock (fw) Select subsystem clock as watch timer clock (fw) F88H Address F89H
NOTE: Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock (fxt) is assumed to be 32.768 kHz.
11-37
TIMERS and TIMER/COUNTERS
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Using the Watch Timer
1. Select a subsystem clock as the LCD display clock, a 0.5 second interrupt, and 2 kHz buzzer enable: BITS SMB LD LD BITR LD LD BITS EMB 15 EA,#8H PMG1,EA P0.3 EA,#85H WMOD,EA IEW ; P0.3 output mode
2. Sample real-time clock processing method: CLOCK BTSTZ RET * * * ; Increment HOUR, MINUTE, SECOND IRQW ; 0.5 second check ; No, return ; Yes, 0.5 second interrupt generation
11-38
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROLLER/DRIVER
12
OVERVIEW
LCD CONTROLLER/DRIVER
The S3C72P9 microcontroller can directly drive an up-to-896-dot (56 segments x 16 commons) LCD panel. Its LCD block has the following components: -- LCD controller/driver -- Display RAM for storing display data -- 56 segment output pins (SEG0-SEG55) -- 16 common output pins (COM0-COM15) -- Five LCD operating power supply pins (VLC1-VLC5) -- VLC5 pin for controlling the driver and bias voltage To use the LCD controller, bit 2 in the watch mode register WMOD must be set to 1, because LCDCK is supplied by the watch timer. The frame frequency, duty and bias, and the segment pins used for display output, are determined by bit settings in the LCD mode register, LMOD. The LCD control register, LCON, is used to turn the LCD display on and off, to switch current to the dividing resistors for the LCD display, and to output LCD clock (LCDCK) and synchronizing signal (LCDSY) for LCD display expansion. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control. When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and idle modes.
VLC1-VLC5 5 COM0-COM7 8 LCD Controller/ Driver COM8-COM11/P4.0-P4.3 4 COM12-COM15/P5.0-P5.3 4 SEG0-SEG39 40 SEG40-SEG55/P9.3-P6.0 16 Data Bus
8
Figure 12-1. LCD Function Diagram
12-1
LCD CONTROLLER/DRIVER
S3C72P9/P72P9 (Preliminary Spec)
Port Latch
16
SEG55/P6.0 SEG54/P6.1 Display RAM (Bank 2) 224 MUX 56 Selector SEG40/P9.3
SEG0 fLCD Data Bus Port Latch 8
LMOD
Timing Controller
COM Control
COM15/P5.3 COM14/P5.2 COM0
LCNST
Contrast Controller LCD Voltage Control VCL5 VCL1
LCON
LCDSY
LCDCK P2.1 Latch P2.2 Latch PM2.1 PM2.2
Figure 12-2. LCD Circuit Diagram
12-2
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA RAM addresses of bank 2 are used as LCD data memory. These locations can be addressed by 1-bit, 4-bit, or 8bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG55 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
S E G 0
S E G 1
S E G 2
S E G 3
S E G 4
S E G 5
S E G 6
S E G 7
S E G 8
S E G 9
S E G 10
S E G 11
S E G 52
S E G 53
S E G 54
S E G 55
b0 b1 b2 b3 b0 b1 b2 b3 b0 b1 b2 b3 COM0 COM1 COM2 COM3 200H 210H 220H 230H 201H 211H 221H 231H 202H 212H 222H 232H
b0 b1 b2 b3 20DH 21DH 22DH 23DH
COM12 COM13 COM14 COM15
2C0H 2D0H 2E0H 2F0H
2C1H 2D1H 2E1H 2F1H
2C2H 2D2H 2E2H 2F2H
2CDH 2DDH 2EDH 2FDH
Figure 12-3. LCD Display Data RAM Organization Table 12-1. Common and Segment Pins per Duty Cycle Duty 1/16 1/12 1/8 Common Pins COM0 - COM15 COM0 - COM11 COM0 - COM7 Segment Pins 40 pins-56 pins Dot Number 640 dots-896 dots 480 dots-672 dots 320 dots-448 dots
NOTE: When 1/8 duty is selected, COM8-COM15 (P4.0-P5.3) can be used for normal I/O pins. When 1/12 duty is selected, COM12 - COM15(P5.0-P5.3)can be used for normal I/O pins.
12-3
LCD CONTROLLER/DRIVER
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROL REGISTER (LCON) The LCD control register (LCON) is used to turn the LCD display on and off, to output LCD clock (LCDCK) and synchronizing signal (LCDSY) for LCD display expansion, and to control the flow of current to dividing resistors in the LCD circuit. Following a RESET, all LCON values are cleared to "0". This turns the LCD display off and stops the flow of current to the dividing resistors. F8EH LCON.3 LCON.2 LCON.1 LCON.0
The effect of the LCON.0 setting is dependent upon the current setting of bits LMOD.0 and LMOD.1. Bit 1 in the LCON is used for contrast control application. Table 12-2. LCD Control Register (LCON) Organization LCON Bit LCON.3 LCON.2 LCON.1 LCON.0 0 0 1 1 Setting 0 1 0 1 0 1 0 1 Description Select duty by means of LMOD.2 - .0 Select 1/12 duty (COM0 - COM11 is selected) Disable LCDCK and LCDSY signal outputs. Enable LCDCK and LCDSY signal outputs. LCD display off; cut off current to dividing resistor LCD display on; application with internal contrast control LCD display on; application with external contrast control LCD display on
NOTE: If the external variable resistor for control connected to VLC5, you can select only one contrast control method(External or Internal contrast control).
Table 12-3. LMOD.1-0 Bits Settings LMOD.1-0 0, 0 0, 1 1, 1 COM0-COM15 SEG0-SEG55 SEG40/P9.3-SEG55/P6.0 Normal I/O port function Power Supply to the Dividing Resistor On
All of the LCD dots off All of the LCD dots on Common and segment signal output corresponds to display data (normal display mode)
12-4
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROLLER/DRIVER
LCD MODE REGISTER (LMOD) The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and display on/off. LMOD can be manipulated using 8-bit write instructions. F8CH F8DH LMOD.3 LMOD.7 LMOD.2 LMOD.6 LMOD.1 LMOD.5 LMOD.0 LMOD.4
The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This is also referred to as the 'frame frequency. Since LCDCK is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the LCD display is turned on. RESET clears the LMOD register values to logic zero. The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. The LCD mode register LMOD controls the output mode of the 16 pins used for normal outputs (P9.3-P6.0). Bits LMOD.7-5 define the segment output and normal bit output configuration. Table 12-4. LCD Clock Signal (LCDCK) Frame Frequency LCDCK Display Duty Cycle 1/8 1/12 1/16
NOTE:
256 Hz 32 - -
512 Hz 64 42.7 32
1024 Hz 128 85.3 64
2048 Hz 256 170.7 128
4096 Hz - 341.3 256
COM0
1 Frame
12-5
LCD CONTROLLER/DRIVER
S3C72P9/P72P9 (Preliminary Spec)
Table 12-5. LCD Mode Register (LMOD) Organization Segment/Port Output Selection Bits LMOD.7 LMOD.6 LMOD.5 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 SEG40-43 SEG port SEG port SEG port SEG port Normal port SEG44-47 SEG port SEG port SEG port Normal port Normal port SEG48-51 SEG port SEG port Normal port Normal port Normal port SEG52-55 SEG port Normal port Normal port Normal port Normal port Total Number of Segment 56 52 48 44 40
NOTE: Segment pins that also can used for normal I/O should be configured to output mode when the SEG function is used.
LCD Clock Selection Bits LMOD.4 0 0 1 1 LMOD.3 1/8 duty (COM0-COM7) 0 1 0 1 fxx/27 (256 Hz) fxx/26 (512 Hz) fxx/25 (1024 Hz) fxx/24 (2048 Hz) LCD Clock (LCDCK) 1/12 duty (COM0-COM11) fxx/26 (512 Hz) fxx/25 (1024 Hz) fxx/24 (2048 Hz) fxx/23 (4096 Hz) 1/16 duty (COM0-COM15) fxx/26 (512 Hz) fxx/25 (1024 Hz) fxx/24 (2048 Hz) fxx/23 (4096 Hz)
NOTE: LCDCK is supplied only when the watch timer is operating. To use the LCD controller, you must set bit 2 in the watch mode register WMOD to "1"
Duty Selection Bits LMOD.2 0 1 Duty 1/8 duty (COM0-COM7 select) 1/16 duty (COM0-COM15 select)
NOTE: When 1/16 duty is selected, ports 4 and 5 should be configured as output mode; when 1/8 duty is selected, ports 4 and 5 can be used as normal I/O ports.
Display Mode Selection Bits LMOD.1 0 0 1 LMOD.0 0 1 1 Function All LCD dots off All LCD dots on Normal display
12-6
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROLLER/DRIVER
LCD CONTRAST CONTROL REGISTER (LCNST) The LCD contrast control register LCNST is used to control the LCD contrast up to 16 step contrast level. Following a RESET, all LCNST values are cleared to "0". F8AH F8BH LCNST.3 LCNST.7 LCNST.2 "0" LCNST.1 "0" LCNST.0 "0"
Table 12-6. LCD Clock Signal (LCDCK) Frame Frequency Enable/Disable LCD Contrast Control Bit (LCNST.7) 0 1 Disable LCD contrast control Enable LCD contrast control
Bits 6-4 0 Always logic zero
LCD Control Level Control Bits (16 steps) LCNST.3 0 0 0 LCNST.2 0 0 0 LCNST.1 0 0 1 LCNST.0 0 1 0 2/16 step 3/16 step 16 Step Regulation Voltage Level 1/16 step (The dimmest level)
. . .
1 1 1 1 16/16 step (The brightest level)
NOTE: VLCD = VDD x (n+17)/32, where n = 0-15.
12-7
LCD CONTROLLER/DRIVER
S3C72P9/P72P9 (Preliminary Spec)
LCD VOLTAGE DIVIDING RESISTORS On-chip voltage dividing resistors for the LCD drive power supply are fixed to the VLC1-VLC5 pins. Power can be supplied without an external dividing resistor. Figure 12-4 shows the bias connections for the S3C72P9 LCD drive power supply. To cut off the flow of current through the dividing resistor, clear bits 0 and 1 of the LCON register.
1/4 Bais
1/5 Bais VCL1 VCL2 VCL3 VCL4 VCL5
S3C72P9
S3C72P9
VCL1 VCL2 VCL3 VCL4 VCL5
Figure 12-4. LCD Bias Circuit Connection
12-8
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROLLER/DRIVER
S3C72P9 Interval Voltage Dividing Resistor VDD
VLC1 VLC2 VLC3 VLC4 VLC5
LCON.1 Contrast Controller "0" "1" LCD contrast control enable bit (LCNST.7) LCON.0 16 steps of voltages
Variable Resistor for Brightness Control
VSS
VSS
NOTES: 1. When the LCD module is turned off, clear LCON.0 and LCON.1 to "0" to reduce power consumption. 2. If an external variable is uesd to connect VLC5 to ground, you can control LCD contrast using the variable resistor.
Figure 12-5. Internal Voltage Dividing Resistor and Contrast Control Circuit (1/5 Bias, Display On)
12-9
LCD CONTROLLER/DRIVER
S3C72P9/P72P9 (Preliminary Spec)
COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. -- In 1/8 duty mode, COM0-COM7 pins are selected -- In 1/12 duty mode, COM0-COM11 pins are selected. -- In 1/16 duty mode, COM0-COM15 pins are selected. When 1/8 duty is selected by clearing LMOD.2 to zero, COM8-COM15 (P4.0-P5.3) can be used for normal I/O port. When 1/12 duty is selected by setting LCON.3 to one, ports 4 should be configured as output mode and port5 can be used for Normal I/O port. SEGMENT (SEG) SIGNALS The 56 LCD segment signal pins are connected to corresponding display RAM locations at bank 2. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.
12-10
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROLLER/DRIVER
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
0123
15 0 1 2 3
15
FR 1 Frame
VDD VSS
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
COM0
VDD VLC1 VLC2 VLC3 VLC4 VLC5
COM1
VDD VLC1 VLC2 VLC3 VLC4 VLC5
COM2
VDD VLC1 VLC2 VLC3 VLC4 VLC5
SEG0
VDD VLC1 VLC2 VLC3 VLC4 VLC5
Figure 12-6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias)
12-11
LCD CONTROLLER/DRIVER
S3C72P9/P72P9 (Preliminary Spec)
0123
15 0 1 2 3
15
FR 1 Frame
VDD VSS
SEG1
VDD VLC1 VLC2 VLC3 VLC4 VLC5
SEG0-COM0
VDD VLC1 VLC2 VLC3 VLC4 VLC5 -VLC4 -VLC3 -VLC2 -VLC1 -VDD
VDD VLC1 VLC2 VLC3 SEG1-COM0 VLC4 VLC5 -VLC4 -VLC3 -VLC2 -VLC1 -VDD
Figure 12-6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued)
12-12
S3C72P9/P72P9 (Preliminary Spec)
LCD CONTROLLER/DRIVER
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
0123456701234567
FR 1 Frame
VDD VSS
COM0
VDD VLC1 VLC2 (VLC3) VLC4 VLC5
COM1
VDD VLC1 VLC2 (VLC3) VLC4 VLC5
COM2
VDD VLC1 VLC2 (VLC3) VLC4 VLC5
SEG0
VDD VLC1 VLC2 (VLC3) VLC4 VLC5
SEG0-COM0
VDD VLC1 VLC2 (VLC3) VLC4 VLC5 -VLC4 -VLC2 (-VLC3) -VLC1 -VDD
Figure 12-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
12-13
LCD CONTROLLER/DRIVER
S3C72P9/P72P9 (Preliminary Spec)
0123456701234567
FR 1 Frame
VDD VSS
SEG1
VDD VLC1 VLC2 (VLC3) VLC4 VLC5
SEG0-COM0
VDD VLC1 VLC2 (VLC3) VLC4 VLC5 -VLC4 -VLC2 (-VLC3) -VLC1 -VDD
Figure 12-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)
12-14
S3C72P9/P72P9 (Preliminary Spec)
SERIAL I/O INTERFACE
13
OVERVIEW
SERIAL I/O INTERFACE
The serial I/O interface (SIO) has the following functional components: -- 8-bit mode register (SMOD) -- Clock selector circuit -- 8-bit buffer register (SBUF) -- 3-bit serial clock counter Using the serial I/O interface, 8-bit data can be exchanged with an external device. The transmission frequency is controlled by making the appropriate bit settings to the SMOD register. The serial interface can run off an internal or an external clock source, or the TOL0 signal that is generated by the 8-bit timer/counter, TC0. If the TOL0 clock signal is used, you can modify its frequency to adjust the serial data transmission rate.
SERIAL I/O OPERATION SEQUENCE
The general operation sequence of the serial I/O interface can be summarized as follows: 1. Set SIO mode to transmit-and-receive or to receive-only. 2. Select MSB-first or LSB-first transmission mode. 3. Set the SCK clock signal in the mode register, SMOD. 4. Set SIO interrupt enable flag (IES) to "1". 5. Initiate SIO transmission by setting bit 3 of the SMOD to "1". 6. When the SIO operation is complete, IRQS flag is set and an interrupt is generated.
13-1
SERIAL I/O INTERFACE
S3C72P9/P72P9 (Preliminary Spec)
Internal Bus 8 SI 8 LSB/MSB SO
SBUF (8-bit)
R IRQS P0.0/SCK Q CK D
Over Flow
TOL0 CPU CLK fxx/210 fxx/24 Clock Selector
Q0 R Q S
Q1
Q2
3-Bit Counter
Clear
SMOD.7 SMOD.6 SMOD.5
-
SMOD.3 SMOD.2 SMOD.1 SMOD.0
8 Internal Bus
BITS (note)
NOTE: Instruction Execution
Figure 13-1. Serial I/O Interface Circuit Diagram
13-2
S3C72P9/P72P9 (Preliminary Spec)
SERIAL I/O INTERFACE
SERIAL I/O MODE REGISTER (SMOD) The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface. Its reset value is logical zero. SMOD is organized in two 4-bit registers, as follows: FE0H FE1H SMOD.3 SMOD.7 SMOD.2 SMOD.6 SMOD.1 SMOD.5 SMOD.0 0
SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in transmit-and-receive mode or receive-only mode. SMOD is a write-only register and can be addressed only by 8bit RAM control instructions. One exception to this is SMOD.3, which can be written by a 1-bit RAM control instruction. When SMOD.3 is set to 1, the contents of the serial interface interrupt request flag, IRQS, and the 3bit serial clock counter are cleared, and SIO operations are initiated. When the SIO transmission starts, SMOD.3 is cleared to logical zero. Table 13-1. SIO Mode Register (SMOD) Organization SMOD.0 SMOD.1 SMOD.2 0 1 0 1 0 1 SMOD.3 SMOD.4 SMOD.7 0 1 0 SMOD.6 0 Most significant bit (MSB) is transmitted first Least significant bit (LSB) is transmitted first Receive-only mode Transmit-and-receive mode Disable the data shifter and clock counter; retain contents of IRQS flag when serial transmission is halted Enable the data shifter and clock counter; set IRQS flag to "1" when serial transmission is halted Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero Bit not used; value is always "0" SMOD.5 0 Clock Selection External clock at SCK pin R/W Status of SBUF SBUF is enabled when SIO operation is halted or when SCK goes high. Enable SBUF read/write SBUF is enabled when SIO operation is halted or when SCK goes high.
0 0 1
0 1 0
1 x 0
Use TOL0 clock from TC0 CPU clock: fxx/4, fxx/8, fxx/64 4.09 kHz clock: fxx/210
1
1
1
262 kHz clock: fxx/24
NOTES: 1. 'fxx' = system clock; 'x' means 'don't care.' 2. kHz frequency ratings assume a system clock (fxx) running at 4.19 MHz. 3. The SIO clock selector circuit cannot select a fxx/24 clock if the CPU clock is fxx/64.
4. It must be selected MSB-first or LSB-first transmission mode before loading the data to SBUF.
13-3
SERIAL I/O INTERFACE
S3C72P9/P72P9 (Preliminary Spec)
SERIAL I/O TIMING DIAGRAMS
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS SET SMOD.3
Transmit Complete
Figure 13-2. SIO Timing in Transmit/Receive Mode
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
High SO
Impendence
IRQS SET SMOD.3
Transmit Complete
Figure 13-3. SIO Timing in Receive-Only Mode
13-4
S3C72P9/P72P9 (Preliminary Spec)
SERIAL I/O INTERFACE
SERIAL I/O BUFFER REGISTER (SBUF) The serial I/O buffer register ,SBUF, can be read or written using 8-bit RAM control instructions. Following a RESET, the value of SBUF is undetermined. When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer register are output to the SO pin (P0.1) at the rate of one bit for each falling edge of the SIO clock. Receive data are simultaneously input from the SI pin (P0.2) to SBUF at the rate of one bit for each rising edge of the SIO clock. When receive-only mode is used, incoming data are input to the SIO buffer at the rate of one bit for each rising edge of the SIO clock.
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O
1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fxx/2 and in MSB-first mode: BITS SMB LD LD LD LD LD LD BITS EMB 15 EA,#03H PMG1,EA EA,#0E6H SMOD,EA EA,#48H SBUF,EA SMOD.3
; P0.0 / SCK and P0.1 / SO Output ; ; ; SIO data transfer
SCK/P0.0 SO/P0.1
External Device
[S3C72P9]
2. Use CPU clock to transfer and receive serial data at high speed: BITS SMB LD LD LD LD LD LD BITS BITR BTSTZ JR LD SMB LD EMB 15 EA,#03H PMG1,EA EA,#47H SMOD,EA EA,TDATA SBUF,EA SMOD.3 IES IRQS STEST EA,SBUF 0 RDATA,EA
; P0.0 / SCK and P0.1 / SO Output, P0.2 / SI ; Input
; SIO start
STEST
13-5
SERIAL I/O INTERFACE
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Continued)
3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode: BITS SMB LD LD LD LD LD LD BITS EI BITS . . INTS PUSH PUSH LD SMB XCH SMB LD BITS POP POP IRET SB EA EA,TDATA 15 EA,SBUF 0 RDATA,EA SMOD.3 EA SB ; RDATA Receive data ; SIO start ; EA Receive data ; Store SMB, SRB ; Store EA ; EA Transmit data IES EMB 15 EA,#03H PMG1,EA EA,#87H SMOD,EA EA,TDATA SBUF,EA SMOD.3 ; SIO start ; P0.0 / SCK and P0.1 / SO Output, P0.2/SI Input
SCK/P0.0 SO/P0.1 SI/P0.2
External Device
[S3C72P9]
13-6
S3C72P9/P72P9 (Preliminary Spec)
SERIAL I/O INTERFACE
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Continued)
4. Transmit and receive an external clock in LSB-first mode: BITS SMB LD LD LD LD Input LD LD BITS EI BITS . . INTS PUSH PUSH LD SMB XCH SMB LD BITS POP POP IRET SB EA EA,TDATA 15 EA,SBUF 0 RDATA,EA SMOD.3 EA SB ; RDATA Receive data ; SIO start ; EA Receive data ; Store SMB, SRB ; Store EA ; EA Transmit data IES EA,TDATA SBUF,EA SMOD.3 ; SIO start EMB 15 EA,#02H PMG1,EA EA,#07H SMOD,EA ; P0.1 / SO Output, P0.0 / SCK and P0.2 / SI
SCK/P0.0 SO/P0.1 SI/P0.2
External Device
[S3C72P9] High Speed SIO Transmission
13-7
SERIAL I/O INTERFACE
S3C72P9/P72P9 (Preliminary Spec)
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Concluded)
Use CPU clock to transfer and receive serial data at high speed: BITS SMB LD LD LD LD LD LD BITS BITR STEST BTSTZ JR LD SMB LD EMB 15 EA,#03H PMG1,EA EA,#47H SMOD, EA EA,TDATA SBUF,EA SCMOD.3 IES IRQS STEST EA,SBUF 0 RDATA,EA ; SIO start ; P0.0 / SCK and P0.1 / SO Output, P0.2 / SI Input
13-8
S3C72P9/P72P9 (Preliminary Spec)
ELECTRICAL DATA
14
OVERVIEW
ELECTRICAL DATA
In this section, information on S3C72P9 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C72P9/P72P9 (Preliminary Spec)
Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL Ports 0-9 - One I/O pin active All I/O pins active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 (note) Total for ports 0, 2-9 Operating Temperature Storage Temperature TA TSTG - - + 100 (Peak value) + 60 (note) - 40 to + 85 - 65 to + 150
Duty . C C
Units V V V mA
mA
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage Output Low Voltage VOH Conditions All input pins except those specified below for VIH2-VIH3 Ports 0, 1, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 2-9 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0, 2-9 VDD - 1.0 - Min 0.7VDD 0.8VDD VDD - 0.1 - - Typ - Max VDD VDD VDD 0.3VDD 0.2VDD 0.1 - V V Units V
VOL
-
-
2.0
V
14-2
S3C72P9/P72P9 (Preliminary Spec)
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 XIN, XOUT, XTIN, and RESET VI = 0 V XIN , XOUT, and XTIN VI = 0 V XIN, XOUT, and XTIN VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5 V Port 0-9 VDD = 3 V RL2 VI = 0 V; VDD = 5 V, RESET VDD = 3 V LCD Voltage Dividing Resistor |VDD-COMi| Voltage Drop (i = 0-15) |VDD-SEGx| Voltage Drop (x = 0-55) VLC1 Output Voltage VLC2 Output Voltage VLC3 Output Voltage VLC4 Output Voltage RLCD TA = 25 C - - - - -3 - 20 3 A A VI = VDD Min - Typ - Max 3 Units A
ILIH2 Input Low Leakage Current Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILIL1 ILIL2 ILOH
20
ILOL
-
-
-3
A
RLI
25 50 100 200 25
47 95 220 450 60
100 200 400 800 80
k
k
VDC
- 15 A per common pin
-
-
120
mV
VDS
- 15 A per segment pin
-
-
120
VLC1 VLC2 VLC3 VLC4
LCD clock = 0 Hz, VLC5 = 0 V
0.8VDD-0.2 0.6VDD-0.2 0.4VDD-0.2 0.2VDD-0.2
0.8VDD 0.6VDD 0.4VDD 0.2VDD
0.8VDD+0.2 0.6VDD+0.2 0.4VDD+0.2 0.2VDD+0.2
V
14-3
ELECTRICAL DATA
S3C72P9/P72P9 (Preliminary Spec)
Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current Symbol IDD1 (2) Conditions VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD2 (2) Idle mode; VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz Min - Typ 3.9 2.9 1.8 1.3 1.3 1.2 Max 8.0 5.5 4.0 3.0 2.5 1.8 Units mA
6.0 MHz 4.19 MHz -
0.5 0.44 15.3 6.4 2.5 0.5 0.2 0.1
1.5 1.0 30 15 5 3 3 2 A
VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% SCMOD = 0000B XT = 0V SCMOD = 0100B
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents.
14-4
S3C72P9/P72P9 (Preliminary Spec)
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
Stabilization time (2)
Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3.0 V. -
-
-
4
ms
Crystal Oscillator
XIN
XOUT
Oscillation frequency (1)
0.4
-
6.0
MHz
C1
C2
Stabilization time (2)
VDD = 3.0 V VDD = 2.0 V to 5.5 V
- - 0.4
- - -
10 30 6.0
ms
External Clock
XIN
XOUT
XIN input frequency (1)
-
MHz
XIN input high and low level width (tXH, tXL) RC Oscillator
XIN R XOUT
- R = 20 k, VDD = 5 V
83.3 -
- 2
1250 -
ns MHz
Frequency
R = 39 k, VDD = 3 V
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2.
-
1
-
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.
14-5
ELECTRICAL DATA
S3C72P9/P72P9 (Preliminary Spec)
Table 14-4. Recommended Oscillator Constants (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) FCR FCR CCR M5 MC5 MC3 Frequency Range Load Cap (pF) C1 TDK 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
Table 14-5. LCD Contrast Controller Characteristics (TA = - 40 C + 85 C, VDD = 4.5 V to 5.5 V) Parameter Resolution Voltage Accuracy Max Output Voltage (LCNST = #8FH) Symbol - VLCON VLC5 Condition - - VDD=5V Min - - 0 Typ - - - Max 4 200 0.1 Units Bits mV V
14-6
KS57C22532/P22532 (Preliminary Spec)
ELECTRICAL DATA
Table 14-6. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTIN XTOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V
- - 32
1.0 - -
2 10 100
s
External Clock
XTIN XTOUT
XTIN input frequency
(1)
-
kHz
XTIN input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14-7. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
14-7
ELECTRICAL DATA
KS57C22532/P22532 (Preliminary Spec)
Table 14-8. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (note) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0, TCL1 Input Frequency f TI0, f TI1 VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0, TCL1 Input High, Low Width tTIH0, tTIL0 tTIH1, tTIL1 VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V SCK Cycle Time tKCY VDD = 2.7 V to 5.5 V; Input Internal SCK source; Output VDD = 2.0 V to 5.5 V; Input Internal SCK source; Output SCK High, Low Width tKH, tKL VDD = 2.7 V to 5.5 V; Input Internal SCK source; Output VDD = 2.0 V to 5.5 V; Input Internal SCK source; Output SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 2.0 V to 5.5 V; Input VDD = 2.0 V to 5.5 V; Output SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 2.0 V to 5.5 V; Input VDD = 2.0 V to 5.5 V; Output 0.48 1.8 800 650 3200 3800 325 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 150 500 400 400 600 500 - - ns - - ns - - ns - - ns - Min 0.67 0.95 0 - Typ - Max 64 64 1.5 1 - s MHz Units s
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
KS57C22532/P22532 (Preliminary Spec)
ELECTRICAL DATA
Table 14-8. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output Delay for SCK to SO Symbol tKSO Conditions VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 2.0 V to 5.5 V; Input VDD = 2.0 V to 5.5 V; Output Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0, INT1, INT2, INT4, K0-K7 Input 10 10 - - Min - Typ - Max 300 250 1000 1000 - - s s Units ns
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
CPU Clock 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 750 kHz
4.2 MHz 3 MHz
15.6 kHz 1 2 1.8 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) 3 4 5 6 7
Figure 14-1. Standard Operating Voltage Range
14-9
ELECTRICAL DATA
KS57C22532/P22532 (Preliminary Spec)
Table 14-9. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx
(2)
Max 5.5 10 - - -
Unit V A s ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-10
KS57C22532/P22532 (Preliminary Spec)
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Normal Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction RESET tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
Normal Mode
VDD
VDDDR Execution of STOP Instrction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-11
ELECTRICAL DATA
KS57C22532/P22532 (Preliminary Spec)
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/fxt tXTL tXTH
XTIN
VDD - 0.1 V 0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-12
KS57C22532/P22532 (Preliminary Spec)
ELECTRICAL DATA
1/fTI tTIL tTIH
TCL0
0.8 VDD 0.2 VDD
Figure 14-7. TCL Timing
tRSL
RESET 0.2 VDD
Figure 14-8. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4, K0 to K7
0.8 VDD 0.2 VDD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-13
ELECTRICAL DATA
KS57C22532/P22532 (Preliminary Spec)
tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH
SO
Output Data
Figure 14-10. Serial Data Transfer Timing
14-14
S3C72P9/P72P9 (Preliminary Spec)
MECHANICAL DATA
15
OVERVIEW
-- Pad diagram
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad/pin coordinate data table
15-1
MECHANICAL DATA
S3C72P9/P72P9 (Preliminary Spec)
23.90 0.30 20.00 0.20 0-8
+ 0.10
0.15 - 0.05
17.90 0.30
14.00 0.20
100-QFP-1420C
0.10 MAX
#100
#1 0.65
0.30
+ 0.10 - 0.05
0.15 MAX
0.05 MIN (0.58) 2.65 0.10 3.00 MAX
0.80 0.20
NOTE: Dimensions are in millimeters.
Figure 15-1. 100-QFP-1420C Package Dimensions
15-2
0.80 0.20
S3C72P9/P72P9 (Preliminary Spec)
S3P72P9 OTP
16
OVERVIEW
S3P72P9 OTP
The S3P72P9 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72P9 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72P9 is fully compatible with the S3C72P9, both in function and in pin configuration. Because of its simple programming requirements, the S3P72P9 is ideal for use as an evaluation chip for the S3C72P9.
16-1
S3P72P9 OTP
S3C72P9/P72P9 (Preliminary Spec)
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P9.3/SEG40 P9.2/SEG41 P9.1/SEG42 P9.0/SEG43 P8.3/SEG44 P8.2/SEG45 P8.1/SEG46 P8.0/SEG47 P7.3/SEG48 P7.2/SEG49 P7.1/SEG50 P7.0/SEG51 P6.3/SEG52/K7 P6.2/SEG53/K6 P6.1/SEG54/K5
SEG4 SEG3 SEG2 SEG1 SEG0 VLC5 VLC4 VLC3 VLC2 VLC1 P0.0/SCK/K0 P0.1/SO/K1 SDAT/P0.2/SI/K2 SCLK/P0.3/BUZ/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/LCDCK P2.2/LCDSY P3.0/TCLO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3P72P9
(100-QFP-1420C)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P6.0/SEG55/K4 P5.3/COM15 P5.2/COM14 P5.1/COM13 P5.0/COM12 P4.3/COM11 P4.2/COM10 P4.1/COM9 P4.0/COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 P3.3/TCL1 P3.2/TCL0 P3.1/TCLO0 NOTE: The bolds indicate an OTP pin name.
Figure 16-1. S3P72P9 Pin Assignments (100-QFP Package)
16-2
S3C72P9/P72P9 (Preliminary Spec)
S3P72P9 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.2 Pin Name SDAT Pin No. 13 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
P0.3 TEST
SCLK VPP(TEST)
14 19
I/O I
RESET VDD/VSS
RESET VDD/VSS
22 15/16
I I
Table 16-2. Comparison of S3P72P9 and S3C72P9 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 1.8 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 100 QFP User Program 1 time 100 QFP Programmed at the factory S3P72P9 16 KByte EPROM S3C72P9 16 KByte mask ROM 1.8 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72P9, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection R/W Mode
NOTE: "0" means Low level; "1" means High level.
16-3
S3P72P9 OTP
S3C72P9/P72P9 (Preliminary Spec)
Table 16-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current Symbol IDD1 (2) Conditions VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD2 (2) Idle mode; VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz Min - Typ 3.9 2.9 1.8 1.3 1.3 1.2 Max 8.0 5.5 4.0 3.0 2.5 1.8 Units mA
6.0 MHz 4.19 MHz -
0.5 0.44 15.3 6.4 2.5 0.5 0.2 0.1
1.5 1.0 30 15 5 3 3 2 A
VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% SCMOD = 0000B XT = 0V SCMOD = 0100B
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents.
16-4
S3C72P9/P72P9 (Preliminary Spec)
S3P72P9 OTP
CPU Clock 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 750 kHz
4.2 MHz 3 MHz
15.6 kHz 1 2 1.8 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) 3 4 5 6 7
Figure 16-2. Standard Operating Voltage Range
16-5
S3C72P9/P72P9 (Preliminary Spec)
DEVELOPMENT TOOLS
17
OVERVIEW
SHINE
DEVELOPMENT TOOLS
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM57 The SASM57 is an relocatable assembler for Samsung's S3C7-series microcontrollers. The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value 'FF' is filled into the unused ROM area up to the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all KS57-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. OTPs One time programmable microcontroller (OTP) for the S3C72P9 microcontroller and OTP programmer (Gang) are now available.
17-1
DEVELOPMENT TOOLS
S3C72P9/P72P9 (Preliminary Spec)
IBM-PC AT or Compatible
RS-232C
SMDS2+
PROM/OTP Writer Unit
Target Application System
RAM Break/Display Unit Probe Adapter Bus Trace/Timer Unit
SAM4 Base Unit
POD
TB72P9 Target Board EVA Chip
Power Supply Unit
Figure 17-1. SMDS Product Configuration (SMDS2+)
17-2
S3C72P9/P72P9 (Preliminary Spec)
DEVELOPMENT TOOLS
TB72P9 TARGET BOARD The TB72P9 target board is used for the S3C79P9 microcontroller. It is supported by the SMDS2+ development system.
TB72P9
To User_VCC Off RESET U2 74HC11 On Stop Idle VCC
+
+
XT1 25 XTAL 100-Pin Connector MDS J101 J101
1 50-Pin Connector 160 QFP S3E72P0 EVA Chip
2
1 50-Pin Connector
GND 2 50 SM1255A
1
External Triggers Ch1 XTAL Ch2
XT1 49 MDS 50 49
Figure 17-2. TB72P9 Target Board Configuration
17-3
DEVELOPMENT TOOLS
S3C72P9/P72P9 (Preliminary Spec)
Table 17-1. Power Selection Settings for TB72P9 'To User_Vcc' Settings
To User_VCC Off On TB72P9 VCC VSS VCC SMDS2/SMDS2+ To User_VCC Off On TB72P9 Target System
Operating Mode
Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system.
External VCC VSS
Target System
The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
VCC SMDS2+
Table 17-2. Main-Clock Selection Settings for TB72P9 Main Clock Setting
XI MDS XTAL
Operating Mode
EVA Chip S3E72P0 XOUT No Connection 100 Pin Connector SMDS2/SMDS2+
Comments Set the XIN switch to "MDS" when the target board is connected to the SMDS2/SMDS2+.
XIN
XI MDS XTAL EVA Chip S3E72P0 XOUT XTAL Target Board
Set the XIN switch to "XTAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+.
XIN
17-4
S3C72P9/P72P9 (Preliminary Spec)
DEVELOPMENT TOOLS
Table 17-3. Sub-Clock Selection Settings for TB72P9 Sub Clock Setting
XTI MDS XTAL
Operating Mode
EVA Chip S3E72P0 XTOUT No Connection 100 Pin Connector SMDS2/SMDS2+
Comments Set the XTI switch to "MDS" when the target board is connected to the SMDS2/SMDS2+.
XTIN
XTI MDS XTAL EVA Chip S3E72P0 XTOUT XTAL Target Board
Set the XTI switch to "TAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+.
XTIN
Table 17-4. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part
External Triggers Ch1 Ch2
Comments
Connector from External Trigger Sources of the Application System
You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. IDLE LED This LED is ON when the evaluation chip (S3E72P0) is in idle mode. STOP LED This LED is ON when the evaluation chip (S3E72P0) is in stop mode.
17-5
DEVELOPMENT TOOLS
S3C72P9/P72P9 (Preliminary Spec)
J101 SEG4 SEG2 SEG0 VLC4 VLC2 P0.0/SCK/K0 P0.2/SI/K2 VDD XOUT TEST XTOUT P1.0/INT0 P1.2/INT2 P2.0/CLO P2.2/LCDSY P3.1/TCLO1 P3.3/TCL1 COM1 COM3 COM5 COM7 P4.1/COM9 P4.3/COM11 P5.1/COM13 P5.3/COM15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 P6.1/SEG54/K5 SEG3 P6.3/SEG52/K7 SEG1 P7.1/SEG50 VLC5 P7.3/SEG48 VLC3 P8.1/SEG46 VLC1 P8.3/SEG44 P0.1/SO/K1 P9.1/SEG42 P0.3/BUZ/K3 P9.3/SEG40 VSS SEG38 XIN SEG36 XTIN SEG34 RESET SEG32 P1.1/INT1 SEG30 P1.3/INT4 SEG28 P2.1/LCDCK SEG26 P3.0/TCLO0 SEG24 P3.2/TCL0 SEG22 COM0 SEG20 COM2 SEG18 COM4 SEG16 COM6 SEG14 P4.0/COM8 SEG12 P4.2/COM10 SEG10 P5.0/COM12 SEG8 P5.2/COM14 SEG6 P6.0/SEG55/K4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
J102 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 P6.2/SEG53/K6 P7.0/SEG51 P7.2/SEG49 P8.0/SEG47 P8.2/SEG45 P9.0/SEG43 P9.2/SEG41 SEG39 SEG37 SEG35 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5
Target Board J101 50-Pin DIP Connector 1 2 J102 1 2 Target Cable for 50-Pin Connector Part Name: (AS50D-A) Order Cods: SM6305 49 50 49 50
Figure 17-4. TB72P9 Adapter Cable for 100 QFP Package (S3C72P9)
50-Pin DIP Connector
50-Pin DIP Connector
2 1 50 49
Figure 17-3. 50-Pin Connectors for TB72P9
Target System J102 1 J101 50-Pin DIP Connector 2
49
50
17-6

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